CY8C21634 Datasheet, PDF (16/42 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 9. Register Map 0 Table: User Space (continued)
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
DBB00DR2
22
RW
PWM_CR
DBB00CR0
23
#
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
DCB02DR1
29
W
ADC1_CR
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
31
32
ACE00CR1
33
ACE00CR2
34
35
36
ACE01CR1
37
ACE01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and must not be accessed.
60
RW
A0
INT_MSK0
61
RW
A1
INT_MSK1
62
RW
A2
INT_VC
63
A3
RES_WDT
64
#
A4
65
A5
66
RW
A6
DEC_CR0
67
A7
DEC_CR1
68
#
A8
69
#
A9
6A
AA
6B
AB
6C
RW
AC
6D
RW
AD
6E
RW
AE
6F
RW
AF
70
RDI0RI
B0
RW
71
RDI0SYN
B1
RW
72
RW
RDI0IS
B2
RW
73
RW
RDI0LT0
B3
RW
74
RDI0LT1
B4
RW
75
RDI0RO0
B5
RW
76
RW
RDI0RO1
B6
RW
77
RW
B7
CPU_F
78
B8
79
B9
7A
BA
7B
BB
7C
BC
7D
BD
DAC_D
7E
BE
CPU_SCR1
7F
BF
CPU_SCR0
# Access is bit specific.
E0
RW
E1
RW
E2
RC
E3
W
E4
E5
E6
RW
E7
RW
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
RL
F8
F9
FA
FB
FC
FD
RW
FE
#
FF
#
Table 10. Register Map 1 Table: Configuration Space
PRT0DM0 00 RW
40
PRT0DM1 01 RW
41
PRT0IC0
02 RW
42
PRT0IC1
03 RW
43
PRT1DM0 04 RW
44
PRT1DM1 05 RW
45
PRT1IC0
06 RW
46
PRT1IC1
07 RW
47
PRT2DM0 08 RW
48
PRT2DM1 09 RW
49
PRT2IC0
0A RW
4A
PRT2IC1
0B RW
4B
PRT3DM0 0C RW
4C
PRT3DM1 0D RW
4D
PRT3IC0
0E RW
4E
PRT3IC1
0F RW
4F
10
50
11
51
12
52
13
53
14
54
Blank fields are Reserved and must not be accessed.
Document Number: 38-12025 Rev. *L
ASE10CR0 80 RW
81
82
83
ASE11CR0 84 RW
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
# Access is bit specific.
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
GDI_O_IN D0 RW
GDI_E_IN
D1 RW
GDI_O_OU D2 RW
GDI_E_OU D3 RW
D4
Page 16 of 42
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