CY8C20134_1106 Datasheet, PDF (27/47 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip Low power at high speed

CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
AC Programming Specifications
Table 28 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ T_A ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ T_A ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ T_A ≤ 85 °C respectively. Typical parameters
apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 28. AC Programming Specifications
Symbol
Description
Min Typ Max Units
Notes
t_RSCLK
t_FSCLK
t_SSCLK
t_HSCLK
F_SCLK
t_ERASEB
t_WRITE
t_DSCLK
t_DSCLK3
t_DSCLK2
t_ERASEALL
Rise time of SCLK
1
–
20
ns
Fall time of SCLK
1
–
20
ns
Data setup time to falling edge of SCLK
40
–
–
ns
Data hold time from falling edge of SCLK
40
–
–
ns
Frequency of SCLK
0
–
8
MHz
Flash erase time (Block)
–
10
–
ms
Flash block write time
–
40
–
ms
Data out delay from falling edge of SCLK
–
–
45
ns 3.6 < V_DD
Data out delay from falling edge of SCLK
–
–
50
ns 3.0 ≤ V_DD ≤ 3.6
Data out delay from falling edge of SCLK
–
–
70
ns 2.4 ≤ V_DD ≤ 3.0
Flash erase time (Bulk)
–
20
–
ms Erase all blocks and protection
fields at once
t_{PROGRAM_HOT} Flash block erase + flash block write time
–
t_{PROGRAM_COLD} Flash block erase + flash block write time
–
–
100
ms 0 °C ≤ T_j ≤ 100 °C
–
200
ms –40 °C ≤ T_j ≤ 0 °C
AC I²C Specifications
Table 29 and Table 30 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C ≤ T_A ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ T_A ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ T_A ≤ 85 °C respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only.
Table 29. AC Characteristics of the I²C SDA and SCL Pins for V_DD ≥ 3.0 V
Symbol
Description
Standard Mode
Min
Max
Fast Mode
Min
Max
Units
F_SCLI2C
t_HDSTAI2C
SCL clock frequency
Hold time (repeated) START condition. After this
period, the first clock pulse is generated
0
100
0
400
kHz
4.0
–
0.6
–
µs
t_LOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
µs
t_HIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
t_SUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
µs
t_HDDATI2C
t_SUDATI2C
Data hold time
Data setup time
0
–
0
–
µs
250
–
100^[23]
–
ns
t_SUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
µs
t_BUFI2C
Bus free time between a STOP and START condition 4.7
–
1.3
–
µs
t_SPI2C
Pulse width of spikes are suppressed by the input filter –
–
0
50
ns
Note
23. A Fast Mode I²C bus device is used in a Standard Mode I²C bus system but the requirement tSU; DAT ≥ 250 ns is met. This automatically is the case if the device
does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I²C bus specification) before the SCL line is released.
Document Number: 001-05356 Rev. *O
Page 27 of 47
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