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CY8C20134_1106 Datasheet, PDF (1/47 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip Low power at high speed | |||
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CY8C20134, CY8C20234, CY8C20334
CY8C20434, CY8C20534, CY8C20634
PSoC® Programmable System-on-Chipâ¢
PSoC® Programmable System-on-Chipâ¢
Features
â Low power CapSense® block
â Configurable capacitive sensing elements
â Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
â Powerful Harvard-architecture processor
â M8C processor speeds running up to 12 MHz
â Low power at high speed
â Operating voltage: 2.4 V to 5.25 V
â Industrial temperature range: â40 °C to +85 °C
â Flexible on-chip memory
â 8 KB flash program storage 50,000 erase/write cycles
â 512-Bytes SRAM data storage
â Partial flash updates
â Flexible protection modes
â Interrupt controller
â In-system serial programming (ISSP)
â Complete development tools
â Free development tool (PSoC Designerâ¢)
â Full-featured, in-circuit emulator, and programmer
â Full-speed emulation
â Complex breakpoint structure
â 128 KB trace memory
â Precision, programmable clocking
â Internal ±5.0% 6- / 12-MHz main oscillator
â Internal low speed oscillator at 32 kHz for watchdog and sleep
â Programmable pin configurations
â Pull-up, high Z, open-drain, and CMOS drive modes on all
GPIOs
â Up to 28 analog inputs on all GPIOs
â Configurable inputs on all GPIOs
â 20-mA sink current on all GPIOs
â Selectable, regulated digital I/O on port 1
⢠3.0 V, 20 mA total port 1 source current
⢠5 mA strong drive mode on port 1 versatile analog mux
â Common internal analog bus
â Simultaneous connection of I/O combinations
â Comparator noise immunity
â Low-dropout voltage regulator for the analog array
â Additional system resources
â Configurable communication speeds
⢠I2C: selectable to 50 kHz, 100 kHz, or 400 kHz
⢠SPI: configurable between 46.9 kHz and 3 MHz
â I2C slave
â SPI master and SPI slave
â Watchdog and sleep timers
â Internal voltage reference
â Integrated supervisory circuit
Logic Block Diagram
PSoC
CORE
Port 3 Port 2 Port 1 Port 0 Config LDO
System Bus
SRAM
512 Bytes
Interrupt
Controller
Global Analog Interconnect
SROM Flash 8K
CPU Core
(M8C)
Sleep and
Watchdog
6/12 MHz Internal Main Oscillator
ANALOG
SYSTEM
CapSense
Block
Analog
Ref.
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Analog
Mux
SYSTEM RESOURCES
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 001-05356 Rev. *O
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised June 13, 2011
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