CY14B512P_12 Datasheet, PDF (27/34 Pages) Cypress Semiconductor – 512-Kbit (64 K × 8) Serial (SPI) nvSRAM with Real Time Clock

CY14B512P
AutoStore or Power-Up RECALL
Over the Operating Range
Parameter
t_FA ^[20]
t_STORE ^[21]
t_DELAY ^[22]
V_SWITCH
t_VCCRISE[23]
V_HDIS[23]
t_LZHSB[23]
t_HHHD[23]
Description
Power-Up RECALL duration
STORE cycle duration
Time allowed to complete SRAM write cycle
Low voltage trigger level
V_CC rise time
HSB output disable voltage
HSB high to nvSRAM active time
HSB high active time
CY14B512P
Min
Max
Unit
–
20
ms
–
8
ms
–
25
ns
–
2.65
V
150
–
µs
–
1.9
V
–
5
µs
–
500
ns
Switching Waveforms
V_CC
V_SWITCH
V_HDIS
Figure 27. AutoStore or Power-Up RECALL^[24]
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
t_VCCRISE
25
Note
t_HHHD
Note²¹
t_STORE
t_LZHSB
t_FA
t_DELAY
t_HHHD
Note²¹ t_STORE
Note ²⁵
t_DELAY
t_LZHSB
t_FA
POWER-UP
RECALL
Read & Write
BROWN POWER-UP
OUT
RECALL
AutoStore
Read & Write
POWER
DOWN
AutoStore
Notes
20. t_FA starts from the time V_CC rises above V_SWITCH.
21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
22. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t_DELAY.
23. These parameters are guaranteed by design and are not tested.
24. Read and write cycles are ignored during STORE, RECALL, and while V_CC is below V_SWITCH.
25. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-53872 Rev. *H
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