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CYV15G0404DXB Datasheet, PDF (26/43 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Transceiver with Reclocker | |||
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PRELIMINARY
CYV15G0404DXB
Maximum Ratings
Above which the useful life may be impaired. User guidelines
only, not tested
Storage Temperature .................................. â65°C to +150°C
Ambient Temperature with
Power Applied............................................. â55°C to +125°C
Supply Voltage to Ground Potential ............... â0.5V to +3.8V
DC Voltage Applied to LVTTL Outputs
in High-Z State .......................................â0.5V to VCC + 0.5V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................â0.5V to VCC + 0.5V
Static Discharge Voltage.......................................... > 2000 V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Power-up Requirements
The CYP(V)15G0404DXB requires one power-supply. The
Voltage on any input or I/O pin cannot exceed the power pin
during power-up.
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
â40°C to +85°C
VCC
+3.3V ±5%
+3.3V ±5%
CYV15G0404DXB DC Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
LVTTL-compatible Outputs
VOHT
Output HIGH Voltage
VOLT
Output LOW Voltage
IOST
Output Short Circuit Current
IOZL
High-Z Output Leakage Current
LVTTL-compatible Inputs
IOH = â 4 mA, VCC = Min.
IOL = 4 mA, VCC = Min.
VOUT = 0V[12], VCC = 3.3V
VOUT = 0V, VCC
2.4
V
0.4
V
â20
â100
mA
â20
20
µA
VIHT
Input HIGH Voltage
VILT
Input LOW Voltage
IIHT
Input HIGH Current
IILT
Input LOW Current
IIHPDT
Input HIGH Current with internal pull-down
IILPUT
Input LOW Current with internal pull-up
LVDIFF Inputs: REFCLKx±
VDIFF[13]
Input Differential Voltage
VIHHP
Highest Input HIGH Voltage
VILLP
Lowest Input LOW voltage
VCOMREF[14] Common Mode Range
3-Level Inputs
REFCLKx Input, VIN = VCC
Other Inputs, VIN = VCC
REFCLKx Input, VIN = 0.0V
Other Inputs, VIN = 0.0V
VIN = VCC
VIN = 0.0V
2.0
â0.5
400
1.2
0.0
1.0
VCC + 0.3 V
0.8
V
1.5
mA
+40
µA
â1.5
mA
â40
µA
+200
µA
â200
µA
VCC
mV
VCC
V
VCC/2
V
VCC â 1.2V V
VIHH
Three-Level Input HIGH Voltage
Min. ⤠VCC ⤠Max.
0.87 * VCC
VCC
V
VIMM
Three-Level Input MID Voltage
Min. ⤠VCC ⤠Max.
0.47 * VCC 0.53 * VCC V
VILL
Three-Level Input LOW Voltage
Min. ⤠VCC ⤠Max.
0.0
0.13 * VCC V
IIHH
Input HIGH Current
VIN = VCC
200
µA
IIMM
Input MID current
VIN = VCC/2
â50
50
µA
IILL
Input LOW current
VIN = GND
â200
µA
Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±
VOHC
Output HIGH Voltage
(Vcc Referenced)
100⦠differential load
150⦠differential load
VCC â 0.5 VCC â 0.2 V
VCC â 0.5 VCC â 0.2 V
12. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
13. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when
the true (+) input is more positive than the complement (â) input. A logic-0 exists when the complement (â) input is more positive than true (+) input.
14. The common mode range defines the allowable range of REFCLKx+ and REFCLKxâ when REFCLKx+ = REFCLKxâ. This marks the zero-crossing between
the true and complement inputs as the signal switches between a logic-1 and a logic-0.
Document #: 38-02097 Rev. **
Page 26 of 43
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