CYV15G0404DXB Datasheet, PDF (14/43 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Transceiver with Reclocker

PRELIMINARY
CYV15G0404DXB
Table 2. Encoder Bypass Mode
Signal Name
TXDx[0] (LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1] (MSB)
Bus Weight
2⁰
2¹
2²
2³
2⁴
2⁵
2⁶
2⁷
2⁸
2⁹
10B Name
a^[7]
b
c
d
e
i
f
g
h
j
When the encoder is enabled, the TXCTx[1:0] data control bits
control the interpretation of the TXDx[7:0] bits and the
characters generated by them. These bits are interpreted as
listed in Table 3.
Table 3. Transmit Modes
TXCTx[1]
0
0
1
1
TX-
CTx[0]
0
1
0
1
Characters Generated
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
Word Sync Sequence
When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a Word Sync Sequence, is generated on
the associated channel. This sequence of K28.5 characters
may start with either a positive or negative disparity K28.5 (as
determined by the current running disparity and the 8B/10B
coding rules). The disparity of the second and third K28.5
characters in this sequence are reversed from what normal
8B/10B coding rules would generate. The remaining K28.5
characters in the sequence follow all 8B/10B coding rules. The
disparity of the generated K28.5 characters in this sequence
follow a pattern of either ++––+–+–+–+–+–+– or
– – ++ – + – + – + – + – + – +.
The generation of this sequence, once started, cannot be
stopped until all 16 characters have been sent. The content of
the associated input registers are ignored for the duration of
this sequence. At the end of this sequence, if the TXCTx[1:0]
= 11 condition is sampled again, the sequence restarts and
remains uninterruptible for the following 15 character clocks.
Transmit BIST
Each transmit channel contains an internal pattern generator
that can be used to validate both the link and device operation.
These generators are enabled by the associated TXBISTx
latch via the device configuration interface. When enabled, a
register in the associated transmit channel becomes a
signature pattern generator by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a 511-
character (or 526-character) sequence that includes all Data
and Special Character codes, including the explicit violation
symbols. This provides a predictable yet pseudo-random
sequence that can be matched to an identical LFSR in the
attached Receiver(s).
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured
for reference clock operation, each pass is preceded by a 16-
character Word Sync Sequence to allow Elasticity Buffer
alignment and management of clock-frequency variations.
Transmit PLL Clock Multiplier
Each Transmit PLL Clock Multiplier accepts a character-rate
or half-character-rate external clock at the associated
REFCLKx± input, and that clock is multiplied by 10 or 20 (as
selected by TXRATEx) to generate a bit-rate clock for use by
the transmit shifter. It also provides a character-rate clock used
by the transmit paths, and outputs this character rate clock as
TXCLKOx.
Each clock multiplier PLL can accept a REFCLKx± input
between 19.5 MHz and 150 MHz, however, this clock range is
limited by the operating mode of the CYV15G0404DXB clock
multiplier (TXRATEx) and by the level on the associated
SPDSELx input.
SPDSELx are 3-level select^[4] inputs that select one of three
operating ranges for the serial data outputs and inputs of the
associated channel. The operating serial signaling-rate and
allowable range of REFCLKx± frequencies are listed in
Table 4.
Table 4. Operating Speed Settings
SPDSELx
LOW
MID (Open)
HIGH
TXRATE
1
0
1
0
1
0
REFCLKx±
Frequency
(MHz)
reserved
19.5 – 40
20 – 40
40 – 80
40 – 75
80 – 150
Signaling
Rate
(MBaud)
195 – 400
400 – 800
800 – 1500
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so it is
necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Document #: 38-02097 Rev. **
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