CYV15G0404DXB Datasheet, PDF (1/43 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Transceiver with Reclocker

PRELIMINARY
CYV15G0404DXB
Independent Clock Quad HOTLink II™ Transceiver
with Reclocker
Features
• Quad channel transceiver for 195- to 1500-MBaud serial
signaling rate
— Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink^® technology
• Compliant to multiple standards
— SMPTE-292M, SMPTE-259M, DVB-ASI, Fibre
Channel, ESCON and Gigabit Ethernet (IEEE802.3z)
— 10 bit uncoded data or 8B/10B coded data
• Truly independent channels
— Each channel can perform reclocker function
— Each channel can operate at a different signaling
rate
— Each channel can transport a different data format
• Internal phase-locked loops (PLLs) with no external
PLL components
• Selectable differential PECL-compatible serial inputs
per channel
— Internal DC-restoration
• Redundant differential PECL-compatible serial outputs
per channel
— No external bias resistors required
— Signaling-rate controlled edge-rates
— Source matched for 50Ω transmission lines
• MultiFrame™ Receive Framer provides alignment
options
— Comma or Full K28.5 detect
— Single or Multi-byte Framer for byte alignment
— Low-latency option
• Selectable input/output clocking options
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low-power 3W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• 0.25µ BiCMOS technology
• JTAG device ID ‘0C811069’x
Functional Description
The CYV15G0404DXB Independent Clock Quad HOTLink II™
Transceiver is a point-to-point or point-to-multipoint communi-
cations building block enabling transfer of data over a variety
of high-speed serial links including SMPTE 292, SMPTE 259
and DVB-ASI video applications. The signaling rate can be
anywhere in the range of 195 to 1500 MBaud per serial link.
Each channel operates independently with its own reference
clock allowing different rates. Each transmit channel accepts
parallel characters in an Input Register, encodes each
character for transport, and then converts it to serial data.
Each receive channel accepts serial data and converts it to
parallel data, decodes the data into characters, and presents
these characters to an Output Register. The received serial
data can also be reclocked and retransmitted through the
serial outputs. Figure 1 illustrates typical connections between
independent video co-processors and corresponding
CYV15G0404DXB chips.
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Independent
Channel
CYV15G0404DXB
Reclocker
Serial Links
Serial Links
Serial Links
Independent
Channel
CYV15G0404DXB
Reclocker
Serial Links
Cable
Connections
Figure 1. HOTLink II™ System Connections
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02097 Rev. **
Revised June 04, 2004