CY14B101KA_11 Datasheet, PDF (26/34 Pages) Cypress Semiconductor – 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock

CY14B101KA
CY14B101MA
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 5. Truth Table for × 8 Configuration
CE
WE
OE
Inputs/Outputs^[55]
H
X
X High Z
L
H
L Data out (DQ₀–DQ₇)
L
H
H High Z
L
L
X Data in (DQ₀–DQ₇)
Mode
Deselect/Power-down
Read
Output disabled
Write
Table 6. Truth Table for × 16 Configuration
CE
WE
OE BHE^[56] BLE^[56]
Inputs/Outputs^[55]
H
X
X
X
X High Z
L
X
X
H
H High Z
L
H
L
L
L Data out (DQ₀–DQ₁₅)
L
H
L
H
L Data out (DQ₀–DQ₇)
DQ₈–DQ₁₅ in High Z
L
H
L
L
H Data out (DQ₈–DQ₁₅)
DQ₀–DQ₇ in High Z
L
H
H
L
L High Z
L
H
H
H
L High Z
L
H
H
L
H High Z
L
L
X
L
L Data in (DQ₀–DQ₁₅)
L
L
X
H
L Data in (DQ₀–DQ₇)
DQ₈–DQ₁₅ in High Z
L
L
X
L
H Data in (DQ₈–DQ₁₅)
DQ₀–DQ₇ in High Z
Mode
Deselect/Power-down
Output disabled
Read
Read
Read
Output disabled
Output disabled
Output disabled
Write
Write
Write
Power
Standby
Active
Active
Active
Power
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Notes
55. Data DQ₀–DQ₇ for × 8 configuration and Data DQ₀–DQ₁₅ for × 16 configuration.
56. BHE and BLE are applicable for × 16 configuration only.
Document #: 001-42880 Rev. *I
Page 26 of 34
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