CYP15G0401RB Datasheet, PDF (25/35 Pages) Cypress Semiconductor – Quad HOTLink II™ Receiver

PRELIMINARY
CYP15G0401RB
Table 11.Package Coordinate Signal Allocation
Ball
ID Signal Name
A01
INC1–
A02
N/C
A03
INC2–
A04
N/C
A05
VCC
A06
IND1–
A07
N/C
A08
GND
A09
IND2–
A10
N/C
A11
INA1–
A12
N/C
A13
GND
A14
INA2–
A15
N/C
A16
VCC
A17
INB1–
A18
N/C
A19
INB2–
A20
N/C
B01
INC1+
B02
N/C
B03
INC2+
B04
N/C
B05
VCC
B06
IND1+
B07
N/C
B08
GND
B09
IND2+
B10
N/C
B11
INA1+
B12
N/C
B13
GND
B14
INA2+
B15
N/C
B16
VCC
B17
INB1+
B18
N/C
B19
INB2+
B20
N/C
C01
TDI
C02
TMS
C03
INSELC
Signal Type
CML IN
NO CONNECT
CML IN
NO CONNECT
POWER
CML IN
NO CONNECT
GROUND
CML IN
NO CONNECT
CML IN
NO CONNECT
GROUND
CML IN
NO CONNECT
POWER
CML IN
NO CONNECT
CML IN
NO CONNECT
CML IN
NO CONNECT
CML IN
NO CONNECT
POWER
CML IN
NO CONNECT
GROUND
CML IN
NO CONNECT
CML IN
NO CONNECT
GROUND
CML IN
NO CONNECT
POWER
CML IN
NO CONNECT
CML IN
NO CONNECT
LVTTL IN PU
LVTTL IN PU
LVTTL IN
Ball
ID Signal Name
C04
INSELB
C05
VCC
C06
PARCTL
C07
SDASEL
C08
GND
C09
N/C
C10
N/C
C11
N/C
C12
N/C
C13
GND
C14
N/C
C15
GND
C16
VCC
C17 TRGRATE
C18
RXRATE
C19
GND
C20
TDO
D01
TCLK
D02
TRSTZ
D03
INSELD
D04
INSELA
D05
VCC
D06 RFMODE
D07
SPDSEL
D08
GND
D09
BRE[3]
D10
BRE[2]
D11
BRE[1]
D12
BRE[0]
D13
GND
D14
N/C
D15
GND
D16
VCC
D17
VCC
D18
RXLE
D19
RFEN
D20
N/C
E01
VCC
E02
VCC
E03
VCC
E04
VCC
E17
VCC
E18
VCC
Signal Type
LVTTL IN
POWER
3-LEVEL SEL
3-LEVEL SEL
GROUND
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
GROUND
NO CONNECT
GROUND
POWER
LVTTL IN PD
LVTTL IN PD
GROUND
LVTTL 3-S OUT
LVTTL IN PD
LVTTL IN PU
LVTTL IN
LVTTL IN
POWER
3-LEVEL SEL
3-LEVEL SEL
GROUND
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
LVTTL IN PU
GROUND
NO CONNECT
GROUND
POWER
POWER
LVTTL IN PU
LVTTL IN PD
NO CONNECT
POWER
POWER
POWER
POWER
POWER
POWER
Ball
ID Signal Name
E19
VCC
E20
VCC
F01
N/C
F02
VCC
F03
VCC
F04 RXCKSEL
F17
BISTLE
F18 RXSTB[1]
F19
RXOPB
F20 RXSTB[0]
G01
GND
G02
GND
G03
GND
G04
GND
G17 DECMODE
G18
GND
G19 FRAMCHAR
G20
RXDB[1]
H01
GND
H02
GND
H03
GND
H04
GND
H17
GND
H18
GND
H19
GND
H20
GND
J01
GND
J02
GND
J03
GND
J04
GND
J17 RXSTB[2]
J18
RXDB[0]
J19
RXDB[5]
J20
RXDB[2]
K01
RXDC[2]
K02 RXCLKC–
K03
GND
K04
LFIC
K17
RXDB[3]
K18
RXDB[4]
K19
RXDB[7]
K20 RXCLKB+
L01
RXDC[3]
Signal Type
POWER
POWER
NO CONNECT
POWER
POWER
3-LEVEL SEL
LVTTL IN PU
LVTTL OUT
LVTTL 3-S OUT
LVTTL OUT
GROUND
GROUND
GROUND
GROUND
3-LEVEL SEL
GROUND
3-LEVEL SEL
LVTTL OUT
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
GROUND
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL I/O PD
LVTTL OUT
Document #: 38-02111 Rev. **
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