CYP15G0401RB Datasheet, PDF (11/35 Pages) Cypress Semiconductor – Quad HOTLink II™ Receiver

PRELIMINARY
CYP15G0401RB
Table 1. Analog Amplitude Detect Valid Signal Levels^[5]
SDASEL Typical signal with peak amplitudes above
LOW 140 mV p-p differential
MID (Open) 280 mV p-p differential
HIGH 420 mV p-p differential
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable. This allows
operation with highly attenuated signals, or in high-noise
environments. This adjustment is made through the SDASEL
signal, a three-level select^[3] input, which sets the trip point for
the detection of a valid signal at one of three levels, as listed
in Table 1. This control input affects the analog monitors for all
receive channels.
The Analog Signal Detect Monitors are active for the Line
Receiver selected by the associated INSELx input.
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLKx) may run at an incorrect rate (depending
on the quality or existence of the input serial data stream).
After a valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP15G0401RB contains four receive channels that can
be independently enabled and disabled. Each channel can be
enabled or disabled separately through the BRE[3:0] inputs,
as controlled by the RXLE latch-enable signal. When RXLE is
HIGH, the signals present on the BRE[3:0] inputs are passed
through the Receive Channel Enable Latch to control the PLLs
and logic of the associated receive channel. The BRE[3:0]
input associated with a specific receive channel is listed in
Table 2.
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received on
a channel, the Transition Detection logic for that channel will
assert LFIx. The LFIx output remains asserted until at least
one transition is detected in each of three adjacent received
characters.
Range Controls
Table 2. BIST and Receive Channel Enable Signal Map
BRE
Input
BRE[3]
BRE[2]
BIST Channel
Enable
(BISTLE)
Receive D
Receive C
Receive PLL
Channel Enable
(RXLE)
Receive D
Receive C
BRE[1]
BRE[0]
Receive B
Receive A
Receive B
Receive A
The Clock/Data Recovery (CDR) circuit includes logic to
monitor the frequency of the Phase Locked Loop (PLL)
Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
• when the incoming data stream resumes after a time in
which it has been “missing”
When RXLE is HIGH and BRE[x] is HIGH, the associated
receive channel is enabled to receive and recover a serial
stream. When RXLE is HIGH and BRE[x] is LOW, the
associated receive channel is disabled and powered down.
Any disabled channel indicates an asserted LFIx output. When
RXLE returns LOW, the values present on the BRE[3:0] inputs
are latched in the Receive Channel Enable Latch, and remain
there until RXLE returns HIGH to open the latch again.^[6]
• when the incoming data stream is outside the acceptable
frequency range
To perform this function, the frequency of the VCO is periodi-
cally sampled and compared to the frequency of the TRGCLK
input. If the VCO is running at a frequency beyond
±1500 ppm^[4] as defined by the training clock frequency, it is
periodically forced to the correct frequency (as defined by
TRGCLK, SPDSEL, and TRGRATE) and then released in an
attempt to lock to the input data stream. The sampling and
relock period of the Range Control is calculated as follows:
RANGE CONTROL SAMPLING PERIOD = (TRGCLK-
PERIOD) * (16000).
During the time that the Range Control forces the PLL VCO to
run at TRGCLK*10 (or TRGCLK*20 when TRGRATE = HIGH)
rate, the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
Clock Multiplier
The Clock Multiplier accepts a character-rate or
half-character-rate external clock at the TRGCLK input, to
generate a character-rate clock for use by the Clock/Data
Recovery (CDR) blocks.
This clock multiplier can accept a TRGCLK input between
20 MHz and 150 MHz (providing the user with the option to
use a TRGCLK frequency at 1/10 or 1/20 the serial bit rate),
however, this clock range is limited by the operating mode of
the CYP15G0401RB clock multiplier (controlled by
TRGRATE) and by the level on the SPDSEL input.
SPDSEL is a static three-level select ^[3] (ternary) input that
selects one of three operating ranges for the serial data inputs.
The operating serial signaling-rate and allowable range of
TRGCLK frequencies are listed in Table 3.
Notes:
4. TRGCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. TRGCLK
must be within ±1500 ppm (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates
the frequency difference between the transmitter and receiver reference clocks to be within ±1500-ppm, the stability of the crystal needs to be within the limits
specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet
compliant, the frequency stability of the crystal needs to be within ±100 ppm.
5. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
6. When a disabled receive channel is re-enabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be
indeterminate for up to 2 ms.
Document #: 38-02111 Rev. **
Page 11 of 35