CYP15G0101DXB Datasheet, PDF (25/39 Pages) Cypress Semiconductor – Single-channel HOTLink II™ Transceiver

CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
CYP(V)(W)15G0101DXB AC Characteristics Over the Operating Range (continued)
Parameter
Description
t_TXCLKF ^{[29, 30, 31]} TXCLK Fall Time
t_TXDS
Transmit Data Set-Up Time to TXCLK↑ (TXCKSEL ≠ LOW)
t_TXDH
Transmit Data Hold Time from TXCLK↑ (TXCKSEL ≠ LOW)
f_TOS
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency
t_TXCLKO
TXCLKO Period
t_TXCLKOD+
TXCLKO+ Duty Cycle with 60% HIGH time
t_{TXCLKOD–}
TXCLKO– Duty Cycle with 40% HIGH time
Receiver LVTTL Switching Characteristics
f_RS
t_RXCLKP
t_RXCLKH
RXCLK Clock Output Frequency
RXCLK Period
RXCLK HIGH Time (RXRATE = LOW)
RXCLK HIGH Time (RXRATE = HIGH)
t_RXCLKL
RXCLK LOW Time (RXRATE = LOW)
RXCLK LOW Time (RXRATE = HIGH)
Min.
0.2
1.7
0.8
19.5
6.66^[28]
–1.0
–0.5
Max.
1.7
150^[27]
51.28
+0.5
+1.0
Unit
ns
ns
ns
MHz
ns
ns
ns
9.75
6.66^[28]
2.33 ^[29]
5.66
2.33 ^[29]
5.66
150^[27]
102.56
26.64
52.28
26.64
52.28
MHz
ns
ns
ns
ns
ns
t_RXCLKD
t_RXCLKR[29]
t_RXCLKF[29]
t_{RXDV–[32]}
t_RXDV+[32]
RXCLK Duty Cycle centered at 50%
–1.0
+1.0 ns
RXCLK Rise Time
0.3
1.2
ns
RXCLK Fall Time
0.3
1.2
ns
Status and Data Valid Time to RXCLK (RXCKSEL = MID)
5UI – 1.5
ns
Status and Data Valid Time to RXCLK (HALF RATE RECOVERED CLOCK) 5UI – 1.0
ns
Status and Data Valid Time From RXCLK (RXCKSEL = MID)
5UI – 1.8
ns
Status and Data Valid Time From RXCLK (HALF RATE RECOVERED CLOCK) 5UI – 2.3
ns
REFCLK Switching Characteristics Over the Operating Range
f_REF
t_REFCLK
t_REFH
REFCLK Clock Frequency
REFCLK Period
REFCLK HIGH Time (TXRATE = HIGH)
REFCLK HIGH Time (TXRATE = LOW)
19.5
6.6^[28]
5.9
2.9^[29]
150^[27]
51.28
MHz
ns
ns
ns
t_REFL
REFCLK LOW Time (TXRATE = HIGH)
REFCLK LOW Time (TXRATE = LOW)
5.9
ns
2.9^[29]
ns
t_REFD[33]
t_REFR[29, ^{30, 31]}
t_REFF[29, ^{30, 31]}
REFCLK Duty Cycle
REFCLK Rise Time (20% – 80%)
REFCLK Fall Time (20% – 80%)
30
70
%
2
ns
2
ns
t_TREFDS
Transmit Data Setup Time to REFCLK (TXCKSEL = LOW)
1.7
ns
t_TREFDH
t_RREFDA[34]
Transmit Data Hold Time from REFCLK (TXCKSEL = LOW)
Receive Data Access Time from REFCLK (RXCKSEL = LOW)
0.8
ns
9.5
ns
t_RREFDV
Receive Data Valid Time from REFCLK (RXCKSEL = LOW)
2.5
ns
t_REFDV–
Received Data Valid Time to RXCLK (RXCKSEL = LOW)
10UI – 4.7
ns
t_REFDV+
Received Data Valid Time from RXCLK (RXCKSEL = LOW)
0.5
ns
t_REFCDV–
Received Data Valid Time to RXCLKC (RXCKSEL = LOW)
10UI – 4.3
ns
t_REFCDV+
t_REFRX[10, ^29]
Received Data Valid Time from RXCLKC (RXCKSEL = LOW)
REFCLK Frequency Referenced to Extracted Received Clock Frequency
–0.2
–1500
ns
+1500 ppm
Notes:
32. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
33. The duty cycle specification is a simultaneous condition with the t_REFH and t_REFL parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30%–70%.
34. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t_RREFDA and set-up
time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx = LOW) could
be used to clock the receive data out of the device.
Document #: 38-02031 Rev. *J
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