CYP15G0101DXB Datasheet, PDF (19/39 Pages) Cypress Semiconductor – Single-channel HOTLink II™ Transceiver

CYP15G0101DXB
CYV15G0101DXB
CYW15G0101DXB
Receive Modes
The operating mode of the receive path is set through the
RXMODE input. The ‘Reserved for test’ setting (RXMODE =
M) is not allowed, even if the receiver is not being used, as it
will stop normal function of the device. When the decoder is
disabled, the RXMODE setting is ignored as long as it is not a
test mode. These modes determine the RXST status
reporting. The different receive modes are listed in Table 12.
Table 12. Receive Operating Modes
RX Mode
Mode
Number
RXMODE
0
L
1
M
2
H
RXST Status Reporting
Status A
Reserved for test
Status B
Power Control
by sequencing the appropriate values on the BOE[1:0] inputs
while the OELE and RXLE signals are raised and lowered. For
systems that do not require dynamic control of power, or want
the part to power up in a fixed configuration, it is also possible
to strap the RXLE and OELE control signals HIGH to perma-
nently enable their associated latches. Connection of the
associated BOE[1:0] signals to a stable HIGH will then enable
the Transmit and Receive channels as soon as the TRSTZ
signal is deasserted.
Output Bus
The receive channel presents a 12-signal output bus
consisting of
• an eight-bit data bus
• a three-bit status bus
• a parity bit.
The bit assignments of the Data and Status are dependent on
the setting of DECMODE. This mapping is shown in Table 13.
The CYP(V)(W)15G0101DXB supports user control of the
powered up or down state of the Transmit and Receive
channel. The Receive channel is controlled by the RXLE
signal and the values present on the BOE[1:0] bus.
The Transmit channel is controlled by the OELE signal and the
values present on the BOE[1:0] bus. If either the Transmit or
the Receive channel is not used, then powering down the
unused channel will save power and reduce system heat
generation. Controlling system power dissipation will improve
the system performance.
Receive Channel
Table 13. Output Register Bit Assignments^[15]
Signal Name
RXST[2] (LSB)
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
DECMODE = LOW
COMDET
DOUT[0]
DOUT[1]
DOUT[2]
DOUT[3]
DOUT[4]
DOUT[5]
DECMODE = MID
or HIGH
RXST[2]
RXST[1]
RXST[0]
RXD[0]
RXD[1]
RXD[2]
RXD[3]
When RXLE = HIGH, the signal on the BOE[0] input directly
controls the power enable for the receive PLL and the analog
circuit. When BOE[0] = HIGH, the Receive channel and its
analog circuits are active. When BOE[0] = LOW, the Receive
channel and its analog circuits are powered down. When
RXLE returns LOW, the values present on the BOE[1:0] inputs
are latched in the Receive Channel Enable Latch. When a
disabled receive channel is re-enabled, the status of the LFI
output and data on the parallel outputs for the Receive channel
may be indeterminate for up to 2 ms.
Transmit Channel
When OELE = HIGH, the signals on the BOE[1:0] inputs
directly control the power enables for the Serial Drivers. When
a BOE[1:0] input is HIGH, the associated Serial Driver is
enabled. When a BOE[1:0] input is LOW, the associated Serial
Driver is disabled. When both Serial Drivers are powered
down, the logic in the entire transmit channel is also powered
down. When OELE returns LOW, the values present on the
BOE[1:0] inputs are latched in the Output Enable Latch.
Device Reset State
When the CYP(V)(W)15G0101DXB is reset by assertion of
TRSTZ, both the Transmit Enable and Receive Enable
Latches are cleared, and the BIST Enable Latch is preset. In
this state, the Transmit and Receive channels are disabled,
and BIST is disabled.
Following a device reset, it is necessary to enable the transmit
and receive channels for normal operation. This can be done
RXD[4]
RXD[5]
RXD[6]
RXD[7] (MSB)
DOUT[6]
DOUT[7]
DOUT[8]
DOUT[9]
RXD[4]
RXD[5]
RXD[6]
RXD[7]
When the 10B/8B Decoder is bypassed (DECMODE = LOW),
the framed 10-bit character is presented to the receiver Output
Register, along with a status output (COMDET) indicating if the
character in the Output Register is one of the selected framing
characters. The bit usage and mapping of the external signals
to the raw 10B transmission character is shown in Table 14.
Table 14. Decoder Bypass Mode (DECMODE = LOW)
Signal Name
Bus Weight
10B Name
RXST[2] (LSB)
COMDET
RXST[1]
2⁰
a
RXST[0]
2¹
b
RXD[0]
2²
c
RXD[1]
2³
d
RXD[2]
2⁴
e
RXD[3]
2⁵
i
RXD[4]
2⁶
f
RXD[5]
2⁷
g
RXD[6]
2⁸
h
RXD[7] (MSB)
2⁹
j
Note:
15. The RXOP output is also driven from the Output Register, but its interpretation is under the separate control of PARCTL.
Document #: 38-02031 Rev. *J
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