CY7C603XX_08 Datasheet, PDF (25/31 Pages) Cypress Semiconductor – enCoRe™ III Low Voltage

CY7C603xx
AC External Clock Specifications
Table 27. 2.7V AC Digital Block Specifications
Function
Description
All
Maximum Block Clocking Frequency
Functions
Timer/
Counter/
PWM
Enable Pulse Width
Maximum Frequency
Dead Band Kill Pulse Width:
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
Maximum Frequency
SPIM
Maximum Input Clock Frequency
Min Typ Max
12.7
100
–
–
–
–
12.7
20
–
–
100
–
–
100
–
–
–
–
12.7
–
–
6.35
SPIS
Maximum Input Clock Frequency
–
–
4.1
Width of SS_ Negated Between Transmis- 100
–
–
sions
Transmitter Maximum Input Clock Frequency
–
–
12.7
Receiver Maximum Input Clock Frequency
–
–
12.7
Unit
Notes
MHz 2.4V < Vdd < 3.0V.
ns
MHz
ns
ns
ns
MHz
MHz
MHz
ns
Maximum data rate at 3.17 MHz due
to 2 x over clocking.
MHz
MHz
Maximum data rate at 1.59 MHz due
to 8 x over clocking.
Maximum data rate at 1.59 MHz due
to 8 x over clocking.
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V and
0°C < T_A < 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 28. 3.3V AC External Clock Specifications
Parameter
Description
F_OSCEXT Frequency with CPU Clock divide by 1
F_OSCEXT Frequency with CPU Clock divide by 2 or
greater
–
High Period with CPU Clock divide by 1
–
Low Period with CPU Clock divide by 1
–
Power Up IMO to Switch
Min Typ Max
0.093 –
12.3
0.186 –
24.6
41.7 –
41.7 –
150 –
5300
–
–
Unit
MHz
MHz
ns
ns
μs
Notes
Maximum CPU frequency is 12 MHz
at 3.3V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
If the frequency of the external clock
is greater than 12 MHz, the CPU
clock divider must be set to 2 or
greater. In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met.
Document #: 38-16018 Rev. *E
Page 25 of 31
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