CY7C1525KV18_12 Datasheet, PDF (24/34 Pages) Cypress Semiconductor – 72-Mbit QDR® II SRAM Two-Word Burst Architecture

CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
AC Electrical Characteristics
Over the Operating Range
Parameter ^[26]
Description
V_IH
Input HIGH voltage
V_IL
Input LOW voltage
Test Conditions
Min
Typ
Max
Unit
V_REF + 0.2 –
–
V
–
– V_REF – 0.2 V
Capacitance
Parameter ^[27]
Description
C_IN
Input capacitance
C_O
Output capacitance
Test Conditions
T_A = 25 C, f = 1 MHz, V_DD = 1.8 V, V_DDQ = 1.5 V
Max
Unit
4
pF
4
pF
Thermal Resistance
Parameter ^[27]
Description
_JA
Thermal resistance
(junction to ambient)
_JC
Thermal resistance
(junction to case)
Test Conditions
165-ball FBGA
Package
Unit
Test conditions follow standard test methods and
13.7
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
3.73
°C/W
°C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
V_REF
OUTPUT
DEVICE
UNDER
TEST
ZQ
(a)
0.75V
Z₀ = 50
R_L = 50
RQ =
250
V_REF = 0.75V
V_REF = 0.75V
V_REF
OUTPUT
DEVICE
UNDER
TEST ^ZQ
INCLUDING
JIG AND
SCOPE
0.75V
RQ =
250
(b)
R = 50
5 pF ^0.25V
ALL INPUT PULSES^[28]
1.25V
0.75V
SLEW RATE= 2 V/ns
Notes
26. Overshoot: V_IH(AC) < V_DDQ + 0.85 V (Pulse width less than t_CYC/2), Undershoot: V_IL(AC) > –1.5 V (Pulse width less than t_CYC/2).
27. Tested initially and after any design or process change that may affect these parameters.
28.
Unless otherwise noted,
pulse levels of 0.25 V to
test conditions are
1.25 V, and output
based on signal transition time of 2 V/ns,
loading of the specified I_OL/I_OH and load
timing reference levels of
capacitance shown in (a)
0.75 V, Vref
of Figure 5.
=
0.75
V,
RQ
=
250
,
V_DDQ
=
1.5
V,
input
Document Number: 001-00436 Rev. *P
Page 24 of 34