CY7C1525KV18_12 Datasheet, PDF (1/34 Pages) Cypress Semiconductor – 72-Mbit QDR® II SRAM Two-Word Burst Architecture

CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
72-Mbit QDR^® II SRAM Two-Word
Burst Architecture
72-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 350 MHz clock for high bandwidth
■ Two-word burst on all accesses
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 700 MHz) at 350 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR^® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Available in × 9, × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core V_DD = 1.8 V (±0.1 V); I/O V_DDQ = 1.4 V to V_DD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Phase Locked Loop (PLL) for Accurate Data Placement
Configurations
CY7C1525KV18 – 8 M × 9
CY7C1512KV18 – 4 M × 18
CY7C1514KV18 – 2 M × 36
Functional Description
The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18
are 1.8 V synchronous pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with 9-bit words
(CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit
words (CY7C1514KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum operating frequency
Maximum operating current
×9
× 18
× 36
350 MHz
350
Not Offered
840
Not Offered
333 MHz
333
790
810
990
300 MHz
300
730
750
910
250 MHz
250
640
650
790
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00436 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 8, 2012