CY8C28243 Datasheet, PDF (23/63 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

PRELIMINARY
CY8C28xxx
CY8C28x33 Register Map Bank 0 Table: User Space
Name
Addr (0,Hex) Access
Name
Addr (0,Hex) Access
PRT0DR
00
RW DBC20DR0
40
#
PRT0IE
01
RW DBC20DR1
41
W
PRT0GS
02
RW DBC20DR2
42
RW
PRT0DM2
03
RW DBC20CR0
43
#
PRT1DR
04
RW DBC21DR0
44
#
PRT1IE
05
RW DBC21DR1
45
W
PRT1GS
06
RW DBC21DR2
46
RW
PRT1DM2
07
RW DBC21CR0
47
#
PRT2DR
08
RW DCC22DR0
48
#
PRT2IE
09
RW DCC22DR1
49
W
PRT2GS
0A
RW DCC22DR2
4A
RW
PRT2DM2
0B
RW DCC22CR0
4B
#
PRT3DR
0C
RW DCC23DR0
4C
#
PRT3IE
0D
RW DCC23DR1
4D
W
PRT3GS
0E
RW DCC23DR2
4E
RW
PRT3DM2
0F
RW DCC23CR0
4F
#
PRT4DR
10
RW
50
PRT4IE
11
RW
51
PRT4GS
12
RW
52
PRT4DM2
13
RW
53
PRT5DR
14
RW
54
PRT5IE
15
RW
55
PRT5GS
16
RW
56
PRT5DM2
17
RW
57
18
58
19
59
1A
5A
1B
5B
1C
5C
1D
5D
1E
5E
1F
5F
DBC00DR0
20
# AMX_IN
60
RW
DBC00DR1
21
W AMUX_CFG
61
RW
DBC00DR2
22
RW CLK_CR3
62
RW
DBC00CR0
23
# ARF_CR
63
RW
DBC01DR0
24
# CMP_CR0
64
#
DBC01DR1
25
W ASY_CR
65
#
DBC01DR2
26
RW CMP_CR1
66
RW
DBC01CR0
27
#
67
DCC02DR0
28
#
68
DCC02DR1
29
W
69
DCC02DR2
2A
RW SADC_DH
6A
RW
DCC02CR0
2B
# SADC_DL
6B
RW
DCC03DR0
2C
# TMP_DR0
6C
RW
DCC03DR1
2D
W TMP_DR1
6D
RW
DCC03DR2
2E
RW TMP_DR2
6E
RW
DCC03CR0
2F
# TMP_DR3
6F
RW
DBC10DR0
30
# ACB00CR3
70
RW
DBC10DR1
31
W ACB00CR0
71
RW
DBC10DR2
32
RW ACB00CR1
72
RW
DBC10CR0
33
# ACB00CR2
73
RW
DBC11DR0
34
# ACB01CR3
74
RW
DBC11DR1
35
W ACB01CR0
75
RW
DBC11DR2
36
RW ACB01CR1
76
RW
DBC11CR0
37
# ACB01CR2
77
RW
DCC12DR0
38
#
78
DCC12DR1
39
W
79
DCC12DR2
3A
RW
7A
DCC12CR0
3B
#
7B
DCC13DR0
3C
#
7C
DCC13DR1
3D
W
7D
DCC13DR2
3E
RW
7E
DCC13CR0
3F
#
7F
Blank fields are Reserved and should not be accessed.
# Access is bit specific.
Name
ASC10CR0
Addr (0,Hex) Access
Name
80
RW RDI2RI
Addr (0,Hex)
C0
ASC10CR1
81
RW RDI2SYN
C1
ASC10CR2
82
RW RDI2IS
C2
ASC10CR3
83
RW RDI2LT0
C3
ASD11CR0
84
RW RDI2LT1
C4
ASD11CR1
85
RW RDI2RO0
C5
ASD11CR2
86
RW RDI2RO1
C6
ASD11CR3
87
RW RDI2DSM
C7
88
C8
89
C9
8A
CA
8B
CB
8C
CC
8D
CD
8E
CE
8F
CF
ASD20CR0
90
RW CUR_PP
D0
ASD20CR1
91
RW STK_PP
D1
ASD20CR2
92
RW
D2
ASD20CR3
93
RW IDX_PP
D3
ASC21CR0
94
RW MVR_PP
D4
ASC21CR1
95
RW MVW_PP
D5
ASC21CR2
96
RW I2C0_CFG
D6
ASC21CR3
97
RW I2C0_SCR
D7
98
I2C0_DR
D8
99
I2C0_MSCR
D9
9A
INT_CLR0
DA
9B
INT_CLR1
DB
9C
INT_CLR2
DC
9D
INT_CLR3
DD
9E
INT_MSK3
DE
9F
INT_MSK2
DF
DEC0_DH
A0
RC INT_MSK0
E0
DEC0_DL
A1
RC INT_MSK1
E1
DEC1_DH
A2
RC INT_VC
E2
DEC1_DL
A3
RC RES_WDT
E3
DEC2_DH
A4
RC
E4
DEC2_DL
A5
RC
E5
DEC3_DH
A6
RC DEC_CR0*
E6
DEC3_DL
A7
RC DEC_CR1*
E7
MUL1_X
A8
W MUL0_X
E8
MUL1_Y
A9
W MUL0_Y
E9
MUL1_DH
AA
R MUL0_DH
EA
MUL1_DL
AB
R MUL0_DL
EB
ACC1_DR1
AC
RW ACC0_DR1
EC
ACC1_DR0
AD
RW ACC0_DR0
ED
ACC1_DR3
AE
RW ACC0_DR3
EE
ACC1_DR2
AF
RW ACC0_DR2
EF
RDI0RI
B0
RW
F0
RDI0SYN
B1
RW
F1
RDI0IS
B2
RW
F2
RDI0LT0
B3
RW
F3
RDI0LT1
B4
RW
F4
RDI0RO0
B5
RW
F5
RDI0RO1
B6
RW
F6
RDI0DSM
B7
RW CPU_F
F7
RDI1RI
B8
RW
F8
RDI1SYN
B9
RW
F9
RDI1IS
BA
RW
FA
RDI1LT0
BB
RW
FB
RDI1LT1
BC
RW DAC1_D
FC
RDI1RO0
BD
RW DAC0_D
FD
RDI1RO1
BE
RW CPU_SCR1
FE
RDI1DSM
BF
RW CPU_SCR0
FF
*Address has a dual purpose, see “Mapping Exceptions” on page 251
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
RW
#
#
Document Number: 001-48111 Rev. *C
Page 23 of 63
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