CY8C28243 Datasheet, PDF (13/63 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

PRELIMINARY
CY8C28xxx
48-Pin Part Pinout
Table 6. 48-Pin Part Pinout (QFN^[12])
Pin
Type
Pin
No. _{Digital Analog} Name
Description
1
IO
I, M P2[3] Direct switched capacitor block input.^[10]
2
IO
I, M P2[1] Direct switched capacitor block input.^[10]
CY8C28623, CY8C28643, and CY8C28645
48-Pin PSoC Devices
3
IO
M
P4[7]
4
IO
M
P4[5]
5
IO
M
P4[3]
6
IO
M
P4[1]
7
Output
SMP Switch Mode Pump (SMP) connection to
external components.
AI, M, P2[3] 1
8
IO
9
IO
10
IO
M
P3[7]
M
P3[5]
M
P3[3]
AI, M, P2[1] 2
M, P4[7] 3
M, P4[5] 4
M, P4[3] 5
11
IO
M
P3[1]
M, P4[1] 6
12
IO
13
IO
14
IO
M
P5[3]
M
P5[1]
M
P1[7] I2C0 Serial Clock (SCL).
SMP 7
M, P3[7] 8
M, P3[5] 9
M, P3[3] 10
15
IO
M
P1[5] I2C0 Serial Data (SDA).
M, P3[1] 11
16
IO
M
P1[3]
M, P5[3] 12
QFN
(Top View)
36 ^{P2[4], M, External AGND}
35 ^{P2[2], M, AI}
34 ^{P2[0], M, AI}
33 ^{P4[6], M}
32 ^{P4[4], M}
31 P4[2], M
30 P4[0], M
29 XRES
28 P3[6], M
27 P3[4], M
26 P3[2], M, I2C1 SCL
25 P3[0], M, I2C1 SDA
17
IO
M
P1[1] Crystal Input (XTALin), I2C0 Serial Clock
(SCL), ISSP-SCLK^[5].
18
Power
Vss Ground connection.
19
IO
20
IO
M
P1[0] Crystal Output (XTALout), I2C0 Serial
Data (SDA), ISSP-SDATA^[5].
M
P1[2] I2C1 Serial Data (SDA).^[8]
21
IO
22
IO
M
P1[4] Optional External Clock Input
(EXTCLK).
M
P1[6] I2C1 Serial Clock (SCL).^[8]
23
IO
M
P5[0]
24
IO
25
IO
26
IO
M
P5[2]
M
P3[0] I2C1 Serial Data (SDA).^[8]
M
P3[2] I2C1 Serial Clock (SCL).^[8]
27
IO
M
P3[4]
28
IO
M
P3[6]
29
Input
XRES Active high external reset with internal
pull down.
30
IO
M
P4[0]
31
IO
32
IO
M
P4[2]
M
P4[4]
Pin
Type
Pin
No. _{Digital Analog} Name
Description
33
IO
34
IO
35
IO
M
P4[6]
41
I, M P2[0] Direct switched capacitor block input.^[11] 42
I, M P2[2] Direct switched capacitor block input.^[11] 43
IO I, M, S
Power
IO I, M, S
P0[6]
Vdd
P0[7]
Analog column mux and SAR ADC
input.^[6]
Supply voltage.
Analog column mux and SAR ADC
input.^[6]
36
IO
M
P2[4] External Analog Ground (AGND).
44 IO IO, M, S P0[5] Analog column mux and SAR ADC
input. Analog column output.^{[6, 7]}
37
IO
M
P2[6] External Voltage Reference (VRef).
45 IO IO, M, S P0[3] Analog column mux and SAR ADC
input. Analog column output.^{[6, 7]}
38
IO I, M, S P0[0] Analog column mux and SAR ADC
input.^[6]
46 IO I, M, S P0[1] Analog column mux and SAR ADC
input.^[6]
39
IO IO, M, S P0[2] Analog column mux and SAR ADC input. 47
IO
Analog column output.^{[6, 9]}
M P2[7]
40
IO IO, M, S P0[4] Analog column mux and SAR ADC input. 48
IO
Analog column output.^{[6, 9]}
M P2[5]
LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input.
Note
12. The QFN package has a center pad that must be connected to ground (Vss)
Document Number: 001-48111 Rev. *C
Page 13 of 63
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