CY8C21234_08 Datasheet, PDF (23/43 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C21634, CY8C21534
CY8C21434, CY8C21334, CY8C21234
Table 21. DC Switch Mode Pump (SMP) Specifications (continued)
Symbol
Description
ΔV_{PUMP_} Load Regulation
Load
Min
Typ
–
5
ΔV_{PUMP_} Output Voltage Ripple (depends on cap/load) –
100
Ripple
E₃
Efficiency
35
50
E₂
Efficiency
35
80
F_PUMP Switching Frequency
DC_PUMP Switching Duty Cycle
–
1.3
–
50
a. L₁ = 2 mH inductor, C₁ = 10 mF capacitor, D₁ = Schottky diode. See Figure 15.
Max
–
–
–
–
–
–
Units
%V_O
mVpp
%
%
MHz
%
Notes
Configuration of footnote.^a V_O
is the “Vdd Value for PUMP
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
Specification, Table 23 on page
24.
Configuration of footnote.^a
Load is 5 mA.
Configuration of footnote.^a
Load is 5 mA. SMP trip voltage
is set to 3.25V.
For I load = 1mA, V_PUMP =
2.55V, V_BAT = 1.3V,
10 uH inductor, 1 uF capacitor,
and Schottky diode.
Figure 15. Basic Switch Mode Pump Circuit
D1
+
V_BAT
L₁
Battery
Vdd
V _{P UMP}
SMP
C1
PSoC
Vss
Document Number: 38-12025 Rev. *M
Page 23 of 43
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