CY7C1380S Datasheet, PDF (22/31 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM

CY7C1380S
CY7C1382S
Switching Waveforms
Figure 5. Read Cycle Timing ^[24]
CLK
ADSP
ADSC
ADDRESS
GW, BWE,
BWx
CE
ADV
OE
Data Out (Q)
t _CYC
tCH
t
CL
tt
ADS ADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
A3
Burst continued with
new base address
tCES tCEH
Deselect
cycle
tADVS tADVH
High-Z
t _CLZ
t _CO
t _OEHZ
Q(A1)
Single READ
ADV
suspends
burst.
tOEV
tCO
t _OELZ
tDOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
BURST READ
Q(A2 + 3)
DON’T CARE
UNDEFINED
t _CHZ
Q(A2)
Q(A2 + 1)
Burst wraps around
to its initial state
Note
24. On this diagram, when CE is LOW: CE₁ is LOW, CE₂ is HIGH and CE₃ is LOW. When CE is HIGH: CE₁ is HIGH or CE₂ is LOW or CE₃ is HIGH.
Document Number: 001-43822 Rev. *F
Page 22 of 31