CY7C1380S Datasheet, PDF (1/31 Pages) Cypress Semiconductor – 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM

CY7C1380S
CY7C1382S
18-Mbit (512 K × 36/1 M × 18) Pipelined
SRAM
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM
Features
■ Supports bus operation up to 167 MHz
■ Available speed grade is 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 3.4 ns (for 167 MHz device)
■ Provides high-performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel^ Pentium^®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1380S available in JEDEC-standard Pb-free 100-pin
TQFP and non Pb-free 165-ball FBGA package and
CY7C1382S available in JEDEC-standard Pb-free 100-pin
TQFP
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
Functional Description
The CY7C1380S/CY7C1382S SRAM integrates 524,288 × 36
and 1,048,576 × 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining chip enable (CE₁), depth-expansion chip
enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP, and
ADV), write enables (BW_X, and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
(ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table on
page 9 for further details). Write cycles can be one to two or four
bytes wide as controlled by the byte write control inputs. GW
when active LOW writes all bytes.
The CY7C1380S/CY7C1382S operates from a +3.3 V core
power supply while all outputs operate with a +2.5 or +3.3 V
power supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
167 MHz Unit
3.4
ns
275
mA
70
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-43822 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 20, 2013