CY7C2168KV18 Datasheet, PDF (21/29 Pages) Cypress Semiconductor – 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2168KV18, CY7C2170KV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter ^[21]
Description
I_DD ^[26]
V_DD operating supply
Test Conditions
Min
Typ
Max
Unit
V_DD = Max, I_OUT = 0 mA, 550 MHz (× 18)
–
f = f_MAX = 1/t_CYC
(× 36)
–
–
650
mA
–
820
450 MHz (× 18)
–
–
560
mA
400 MHz (× 36)
–
–
640
mA
I_SB1
Automatic power down
Max V_DD,
550 MHz (× 18)
–
–
340
mA
current
both ports deselected,
V_IN  V_IH or V_IN  V_IL,
(× 36)
–
–
340
mA
f = f_MAX = 1/t_CYC,
450 MHz (× 18)
–
–
310
mA
inputs static
400 MHz (× 36)
–
–
290
mA
Note
26. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-58923 Rev. *E
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