CY7C2168KV18 Datasheet, PDF (2/29 Pages) Cypress Semiconductor – 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Logic Block Diagram – CY7C2168KV18
CY7C2168KV18, CY7C2170KV18
A_(18:0)
19
LD
K
K
DOFF
V_REF
R/W
BWS_[1:0]
Address
Register
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Read Data Reg.
36
18
18
18
Output
Logic
R/W
Control
Reg.
Reg. ¹⁸
Reg.
18
18
CQ
CQ
DQ_[17:0]
QVLD
Logic Block Diagram – CY7C2170KV18
A_(17:0)
18
LD
K
K
DOFF
V_REF
R/W
BWS_[3:0]
Address
Register
CLK
Gen.
Control
Logic
Document Number: 001-58923 Rev. *E
Write
Reg
Write
Reg
Read Data Reg.
72
36
36
36
Output
R/W
Logic
Control
Reg.
Reg. ³⁶
Reg.
36
36
CQ
CQ
DQ_[35:0]
QVLD
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