CY7C1484V25 Datasheet, PDF (21/26 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

CY7C1484V25
CY7C1485V25
Switching Waveforms (continued)
Figure 3 shows read/write cycle timing waveforms.^{[18, 20, 21]}
Figure 3. Read/Write Cycle Timing
tCYC
CLK
tCH tCL
tADS tADH
ADSP
ADSC
ADDRESS A1
tAS tAH
A2
BWE, BW X
tCES tCEH
CE
A3
A4
tWES tWEH
A5
A6
ADV
OE
Data In (D)
Data Out (Q)
tCO
tDS tDH
High-Z
tCLZ
D(A3)
tOEHZ
High-Z
Q(A1)
Q(A2)
Back-to-Back READs
Single WRITE
DON’T CARE
tOELZ
D(A5) D(A6)
Q(A4) Q(A4+1) Q(A4+2)
BURST READ
Q(A4+3)
UNDEFINED
Back-to-Back
WRITEs
Notes
20. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
21. GW is HIGH.
Document #: 38-05286 Rev. *H
Page 21 of 26
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