CY7C1484V25 Datasheet, PDF (1/26 Pages) Cypress Semiconductor – 72-Mbit (2M x 36/4M x 18) Pipelined DCD Sync SRAM

CY7C1484V25
CY7C1485V25
72-Mbit (2M x 36/4M x 18) Pipelined
DCD Sync SRAM
Features
Functional Description^[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 2.5V core power supply (V_DD)
• 2.5V/1.8V IO supply (V_DDQ)
• Fast clock-to-output times
— 3.0 ns (for 250-MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel^®
Pentium^® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1484V25, CY7C1485V25 available in JEDEC-
standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free
165-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
The CY7C1484V25/CY7C1485V25 SRAM integrates 2M x
36/4M x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE₁), depth-expansion Chip
Enables (CE₂ and CE₃), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW_X and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at the rising edge
of clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle. This part supports byte write
operations (see “Pin Definitions” on page 5 and “Truth Table”
on page 8 for further details). Write cycles can be one to four
bytes wide, as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written. This device incor-
porates an additional pipelined enable register, which delays
turning off the output buffers an additional cycle when a
deselect is executed. This feature allows depth expansion
without penalizing system performance.
The CY7C1484V25/CY7C1485V25 operates from a +2.5V
core power supply while all outputs operate with a +2.5V or a
+1.8V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
200 MHz
167 MHz
Unit
3.0
3.0
3.4
ns
450
450
400
mA
120
120
120
mA
Note
1. For best practices recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05286 Rev. *H
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised April 24, 2007
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