CY14B101Q1_11 Datasheet, PDF (20/26 Pages) Cypress Semiconductor – 1 Mbit (128 K x 8) Serial SPI nvSRAM Infinite read, write, and RECALL cycles

CY14B101Q1
CY14B101Q2
CY14B101Q3
Hardware STORE Cycle
Parameter
t_PHSB
Description
Hardware STORE pulse width
Figure 28. Hardware STORE Cycle^[16]
Write Latch set
HSB (IN)
tPHSB
HSB (OUT)
tDELAY
tSTORE
RWI
CY14B101Q3
Unit
Min
Max
15
–
ns
tHHHD
tLZHSB
Write Latch not set
HSB (IN)
tPHSB
HSB (OUT)
RWI
tDELAY
HSB pin is driven HIGH to VCC only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
Note
16. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document #: 001-50091 Rev. *H
Page 20 of 26
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