CY14B101Q1_11 Datasheet, PDF (1/26 Pages) Cypress Semiconductor – 1 Mbit (128 K x 8) Serial SPI nvSRAM Infinite read, write, and RECALL cycles

CY14B101Q1
CY14B101Q2
CY14B101Q3
1 Mbit (128 K x 8) Serial SPI nvSRAM
Features
■ 1-Mbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 128 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐ RECALL to SRAM initiated on power-up
(Power-Up RECALL) or by SPI instruction
(Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14B101Q1)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■ High speed serial peripheral interface (SPI)
❐ 40 MHz clock rate
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4,1/2, or entire array
■ Low power consumption
❐ Single 3 V +20%, –10% operation
❐ Average active current of 10 mA at 40 MHz operation
■ Industry standard configurations
❐ Industrial temperature
❐ CY14B101Q1 has identical pin configuration to industry
standard 8-pin NV memory
Logic Block Diagram
❐ 8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14B101Q1/CY14B101Q2/CY14B101Q3
combines a 1 Mbit nvSRAM with a nonvolatile element in each
memory cell with serial SPI interface. The memory is organized
as 128 K words of 8 bits each. The embedded nonvolatile
elements incorporate the QuantumTrap technology, creating the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles, while the QuantumTrap cell
provides highly reliable nonvolatile storage of data. Data
transfers from SRAM to the nonvolatile elements (STORE
operation) takes place automatically at power-down (except for
CY14B101Q1). On power-up, data is restored to the SRAM from
the nonvolatile memory (RECALL operation). Both STORE and
RECALL operations can also be initiated by the user through SPI
instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B101Q1
No
Yes
CY14B101Q2
Yes
Yes
CY14B101Q3
Yes
Yes
No
No
Yes
V_CC
V_CAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
128 K X 8
SRAM Array
128 K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
HSB
Instruction
register
Address
Decoder
A0-A16
D0-D7
SI
Data I/O register
SO
Status Register
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-50091 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 18, 2011
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