CY8C41123 Datasheet, PDF (2/36 Pages) Cypress Semiconductor – Linear Power PSoC™ Devices

PRELIMINARY
CY8C41123 and CY8C41223
3.0 Complete Feature List
• Extended Operating Voltage of 2.5V to 36V
• Powerful Harvard Architecture Processor
— M8C Processor Speeds to 24 MHz
— Low Power at High Speed
— Industrial Temperature Range: -40°C to +85°C
• Additional Flexibility for Sleep Modes
— Select when System Resources are Shut Down
— Very Low Current Mode for 100 nA Sleep (Deep Sleep)
• 2 Advanced Power PSoC Blocks
— 2 High Voltage Analog Sense Inputs
— 2 High Voltage Linear Opamp Control Loops for Driving
Power PFETs
• Advanced Analog Blocks
— Analog Absolute Accuracy (0.75%)
— 2 Comparators with DAC References
— 6- to 12-Bit ADC (20 Ksps at 8 Bits)
— Configurable Analog Mux, 10:1 or 5:2 Differential
• 4 Advanced Digital Blocks
— 8- to 16-Bit Timers and Counters
— Connectable to All GPIO Pins
— Complex Peripherals by Combining Blocks
• Flexible On-Chip Memory
— 4KB Flash Program Storage 50,000 Erase/Write Cycles
— 256 Bytes SRAM
— In-System Serial Programming (ISSP™)
— Partial Flash Updates (64-Byte Blocks)
— Flexible Protection Modes
— EEPROM Emulation in Flash
• Precision, Programmable Clocking
• Complete Development Tools
— Free Development Software
(PSoC™ Designer)
— Full-Featured, In-Circuit Emulator and
Programmer
— Full Speed Emulation
— Complex Breakpoint Structure
— 128KB Trace Memory
— Free Application Generation Software
(PSoC Express™)
• Additional System Resources
— I2C™ Master, Slave, and Multi-Master to 400 kHz
— Watchdog and Sleep Timers
— User-Configurable Low Voltage Detection
— Integrated Supervisory Circuit
— On-Chip Precision Voltage Reference
— 4-Bit Current References
3.1 Differences from CY8C42x23
• The CY8C41x23 is a cost-reduced version of the
CY8C42x23 and targets linear-control applications.
• The HVO pin and current DACs have been eliminated and
the PWM with deadband capability has been removed from
the digital blocks.
4.0 PSoC Functional Overview
The key feature set of the Linear Power PSoC family is the
ability to be powered from and connect to voltages above the
standard 5V logic voltage used by most microcontrollers. The
PSoC's HV_dd pin can connect to a supply voltage of up to 36V.
Internally, an LDO regulator converts the supply voltage to 5V
for powering the analog system, digital system, the core, and
the GPIO.
High voltage signals can be connected to the analog circuitry
through one of two selectable attenuators, each having three
ranges. These precision dividers reduce the external analog
voltage by a factor of 4, 8, or 16. This allows single-ended or
differential signals with up to 36V common mode to be
measured with the ADC. The GPIO pins are not high-voltage
tolerant. Signals with voltages exceeding V_GPIO (as shown in
the Absolute Maximum Ratings table, 8.2) cannot be
connected to the GPIO pins (P0 [7:0] and P1 [1:0]). Doing so
will damage the device.
The Linear Power PSoC family consists of several Mixed-
Signal Array with On-Chip Controller devices. These devices
are designed to replace multiple traditional MCU-based
system components with one, low-cost single-chip program-
mable component. A Linear Power PSoC device includes
configurable analog, digital, and power blocks, as well as
programmable interconnects. This architecture allows the user
to create customized peripheral configurations, to match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.
The PSoC architecture, as illustrated in Figure 2-1, is
comprised of five main areas: the Core, the System
Resources, the Digital System, the Analog System, and the
Power Control System. Configurable global bus resources
allow all the device resources to be combined into a complete
custom system. Each PSoC device includes 4 digital blocks
and up to 10 general purpose IO (GPIO). The GPIO provide
access to the global digital and analog interconnects.
4.1 Linear Power PSoC Core
The Linear Power PSoC Core is a powerful engine that
supports a rich instruction set. It encompasses SRAM for data
storage, an interrupt controller, sleep and watchdog timers,
and IMO (internal main oscillator) and ILO (internal low-speed
oscillator). The CPU core, called the M8C, is a powerful
processor with speeds up to 24 MHz. The M8C is a four MIPS
8-bit Harvard architecture microprocessor.
System Resources provide additional capability, such as
digital clocks for increased flexibility of the PSoC mixed-signal
arrays; I2C functionality for implementing master, slave, and
multi-master; an internal voltage reference of 1.3V for a
number of analog PSoC subsystems; and various system
resets supported by the M8C.
Document 001-00360 Rev. *A
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