S29GL01GT Datasheet, PDF (18/105 Pages) Cypress Semiconductor – 1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte)

S29GL01GT, S29GL512T
4. Read Operations
4.1 Asynchronous Read
Each read access may be made to any location in the memory (random access). Each random access is self-timed with the same
latency from CE# or address to valid data (t_ACC or t_CE).
4.2 Page Mode Read
Each random read accesses an entire 32-byte Page in parallel. Subsequent reads within the same Page have faster read access
speed. The Page is selected by the higher address bits (Amax-A4), while the specific word of that Page is selected by the least
significant address bits A3-A0 (A3-A-1 in x8 mode). The higher address bits are kept constant and only A3-A0 (A3-A-1 in x8 mode)
changed to select a different word in the same Page. This is an asynchronous access with data appearing on DQ15-DQ0 (DQ7-DQ0
in x8 mode) when CE# remains Low, OE# remains Low, and the asynchronous Page access time (t_PACC) is satisfied. If CE# goes
High and returns Low for a subsequent access, a random read access is performed and time is required (t_ACC or t_CE).
Document Number: 002-00247 Rev. *G
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