CY7C1546V18 Datasheet, PDF (18/27 Pages) Cypress Semiconductor – 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
Boundary Scan Order
Bit Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Bump ID
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
Bit Number
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Bump ID
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
8B
7C
6C
8A
7A
7B
6B
Bit Number
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
Bit Number
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Bump ID
1J
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Internal
Document Number: 001-06550 Rev. *D
Page 18 of 27