CY7C1546V18 Datasheet, PDF (15/27 Pages) Cypress Semiconductor – 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

TAP Controller Block Diagram
CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
0
Bypass Register
Selection
TDI
Circuitry
210
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . 2 1 0
Identification Register
108 . ^. . . 2 1 0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range ^{[11, 12, 13]}
Parameter
V_OH1
V_OH2
V_OL1
V_OL2
V_IH
V_IL
I_X
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and Output Load Current
Test Conditions
I_OH = −2.0 mA
I_OH = −100 µA
I_OL = 2.0 mA
I_OL = 100 µA
GND ≤ V_I ≤ V_DD
Min
Max
Unit
1.4
V
1.6
V
0.4
V
0.2
V
0.65V_DD V_DD + 0.3
V
–0.3 0.35V_DD
V
–5
5
µA
Notes
11. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20.
12. Overshoot: V_IH(AC) < V_DDQ + 0.3V (pulse width less than t_CYC/2). Undershoot: V_IL(AC) > − 0.3V (pulse width less than t_CYC/2).
13. All voltage refers to ground.
Document Number: 001-06550 Rev. *D
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