CY7C1546V18 Datasheet, PDF (1/27 Pages) Cypress Semiconductor – 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1546V18
CY7C1557V18
CY7C1548V18
CY7C1550V18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 300 MHz to 375 MHz clock for high bandwidth
■ 2-Word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) at 375 MHz
■ Read latency of 2.0 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Core V_DD = 1.8V ± 0.1V; IO V_DDQ = 1.4V to V_DD[1]
■ HSTL inputs and Variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1546V18 – 8M x 8
CY7C1557V18 – 8M x 9
CY7C1548V18 – 4M x 18
CY7C1550V18 – 2M x 36
Functional Description
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18),
18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18)
that burst sequentially into or out of the device.
Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, that share the same
physical pins with the data inputs, D) are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from individual DDR SRAMs in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
375 MHz
375
x8
1300
x9
1300
x18
1300
x36
1300
333 MHz
333
1200
1200
1200
1200
300 MHz
300
1100
1100
1100
1100
Unit
MHz
mA
Note
1. The QDR consortium specification for V_DDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V_DDQ
= 1.4V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06550 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 7, 2007