CY7C1461AV33_06 Datasheet, PDF (18/29 Pages) Cypress Semiconductor – 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

209-ball FBGA Boundary Scan Order ^{[14, 15]}
CY7C1463AV33(2M x 18), CY7C1465AV33 (512K x 72)
Bit#
Ball ID
Bit#
Ball ID
1
W6
36
F6
2
V6
37
K8
3
U6
38
K9
4
W7
39
K10
5
V7
40
J11
6
U7
41
J10
7
T7
42
H11
8
V8
43
H10
9
U8
44
G11
10
T8
45
G10
11
V9
46
F11
12
U9
47
F10
13
P6
48
E10
14
W11
49
E11
15
W10
50
D11
16
V11
51
D10
17
V10
52
C11
18
U11
53
C10
19
U10
54
B11
20
T11
55
B10
21
T10
56
A11
22
R11
57
A10
23
R10
58
C9
24
P11
59
B9
25
P10
60
A9
26
N11
61
D8
27
N10
62
C8
28
M11
63
B8
29
M10
64
A8
30
L11
65
D7
31
L10
66
C7
32
K11
67
B7
33
M6
68
A7
34
L6
69
D6
35
J6
70
G6
Note:
15. Bit# 138 is preset HIGH.
CY7C1461AV33
CY7C1463AV33
CY7C1465AV33
Bit#
Ball ID
71
H6
72
C6
73
B6
74
A6
75
A5
76
B5
77
C5
78
D5
79
D4
80
C4
81
A4
82
B4
83
C3
84
B3
85
A3
86
A2
87
A1
88
B2
89
B1
90
C2
91
C1
92
D2
93
D1
94
E1
95
E2
96
F2
97
F1
98
G1
99
G2
100
H2
101
H1
102
J2
103
J1
104
K1
105
N6
Bit#
Ball ID
106
K3
107
K4
108
K6
109
K2
110
L2
111
L1
112
M2
113
M1
114
N2
115
N1
116
P2
117
P1
118
R2
119
R1
120
T2
121
T1
122
U2
123
U1
124
V2
125
V1
126
W2
127
W1
128
T6
129
U3
130
V3
131
T4
132
T5
133
U4
134
V4
135
W5
136
V5
137
U5
138
Internal
Document #: 38-05356 Rev. *E
Page 18 of 29
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