CY8CMBR2110 Datasheet, PDF (17/68 Pages) Cypress Semiconductor – CapSense® Express™ 10-Button Controller

CY8CMBR2110
Button Shorted to V_DD
If any button is shorted to V_DD, it is disabled.
Figure 26. Button Shorted to V_DD
V_DD
shorting
Button
CY8CMBR2110
Button to Button Short
If two or more buttons are shorted to each other, all of these
buttons are disabled.
Figure 27. Button to Button Short
Button
shorting
CY8CMBR2110
In Figure 28, CS0 and CS1 are enabled; CS2 and CS3 are
disabled because they failed the POST. Therefore, a 5-ms pulse
is observed on GPO2 and GPO3.
I²C Communication
CI²YC8iCs MthBeRin2t1e1rf0ac(Ie²Cusseladvteo)caonmdmthuenhicoastet (bI^{2eCtwmeaesntethr)e.} It uses a
simple two-wire synchronous communication protocol. These
two wires are:
1. Serial Clock (SCL) – This line is used to synchronize the slave
with the master.
2. Serial Data (SDA) – This line is used to send data between
the master and the slave.
The CY8CMBR2110 can be a part of a one-slave or a multi-slave
environment. See Figure 29 and Figure 30.
Figure 29. I²C Communication between One Master and One
Slave
V_DD
R
I²C Master
(Host)
R
SCL
I²C Slave
SDA ^{(CY8CMBR2110)}
Button
Improper Value of C_MOD
■ Recommended value of C_MOD is 2 nF to 2.4 nF.
■ If the value of C_MOD is less than 1 nF or greater than 4 nF, all
the buttons are disabled.
Button C_P > 40 pF
If the parasitic capacitance (C_P) of any button is more than 40 pF,
that button is disabled.
Figure 28. Example Showing CS0 and CS1 Passing the POST
and CS2 and CS3 Failing
GPO0
(High)
GPO1
(High)
GPO2
GPO3
5ms pulse
5ms pulse
Figure 30. I²C Communication between One Master and
Multiple Slaves
V_DD
R
R
I²C
SCL
Master
(Host)
SDA
I²C
Slave 1
I²C
Slave 2
I²C
Slave 3
CY8CMBR2110
Other slave devices
on the bus
The CY8CMBR2110 I²C interface has the following features:
1. Bit rate up to 100 kbps
2. Configurable I²C slave address (0–127), with default slave
address as ‘37h’.
3. Hardware address compare
4. No bus-stalling – No clock stretching
5. I²C buffer mode (32-byte hardware buffer)
6. Register-based access to I²C master for read and write opera-
tions.
Document Number: 001-74494 Rev. *A
Page 17 of 68