CY28443 Datasheet, PDF (17/25 Pages) Cypress Semiconductor – Clock Generator for Intel® Calistoga Chipset

PRELIMINARY
CY28443
Absolute Maximum Conditions
Parameter
Description
Condition
Min. Max.
V_DD
V_{DD_A}
V_IN
T_S
T_A
T_J
Ø_JC
Ø_JA
ESD_HBM
UL-94
Core Supply Voltage
Analog Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Relative to V_SS
Non-functional
Functional
Functional
Mil-STD-883E Method 1012.1
JEDEC (JESD 51)
MIL-STD-883, Method 3015
At 1/8 in.
–0.5
4.6
–0.5
4.6
–0.5 V_DD + 0.5
–65
150
0
85
–
150
–
20
–
60
2000
–
V–0
MSL
Moisture Sensitivity Level
1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Unit
V
V
VDC
°C
°C
°C
°C/W
°C/W
V
DC Electrical Specifications
Parameter
All VDDs
V_ILI2C
V_IHI2C
V_{IL_FS}
V_{IH_FS}
V_{ILFS_C}
V_{IMFS_C}
V_{IHFS_C}
V_IL
V_IH
I_IL
I_IH
V_OL
V_OH
I_OZ
C_IN
C_OUT
L_IN
V_XIH
V_XIL
I_DD3.3V
Description
3.3V Operating Voltage
Input Low Voltage
Input High Voltage
FS_[A,B] Input Low Voltage
FS_[A,B] Input High Voltage
FS_C Input Low Voltage
FS_C Input Middle Voltage
FS_C Input High Voltage
3.3V Input Low Voltage
3.3V Input High Voltage
Input Low Leakage Current
Input High Leakage Current
3.3V Output Low Voltage
3.3V Output High Voltage
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Xin High Voltage
Xin Low Voltage
Dynamic Supply Current
I_PD3.3V
I_PD3.3V
Power-down Supply Current
Power-down Supply Current
Condition
Min.
Max. Unit
3.3 ± 5%
3.135 3.465 V
SDATA, SCLK
–
1.0
V
SDATA, SCLK
2.2
–
V
Typical
V_SS – 0.3 0.35
V
0.7 V_DD + 0.5 V
V_SS – 0.3 0.35
V
0.7
1.7
V
Typical
2.0 V_DD + 0.5 V
V_SS – 0.3 0.8
V
2.0 V_DD + 0.3 V
Except internal pull-up resistors, 0 < V_IN < V_DD
–5
5
µA
Except internal pull-down resistors, 0 < V_IN < V_DD –
5
µA
I_OL = 1 mA
–
0.4
V
I_OH = –1 mA
2.4
–
V
–10
10
µA
At max load in low drive mode per Figure 14
@133 MHz
PD asserted, Outputs Driven
PD asserted, Outputs Tri-state
3
5
pF
3
6
pF
–
7
nH
0.7V_DD
V_DD
V
0
0.3V_DD V
–
300 mA
–
70 mA
–
5
mA
Document #: 38-07716 Rev *C
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