CY28443 Datasheet, PDF (10/25 Pages) Cypress Semiconductor – Clock Generator for Intel® Calistoga Chipset

PRELIMINARY
CY28443
Byte 11: Control Register 11
Bit
7
6
5
4
3
@Pup
0
HW
HW
HW
0
Name
RESERVED
RESERVED
RESERVED
RESERVED
27MHz
2
0
RESERVED
1
0
RESERVED
0
HW
RESERVED
Byte 12: Control Register 12
Bit
7
@Pup
0
Name
CLKREQ#A
6
0
CLKREQ#B
5
0
RESERVED
4
0
RESERVED
3
0
RESERVED
2
0
RESERVED
1
0
RESERVED
0
0
RESERVED
Byte 13: Control Register 13
Bit
7
6
@Pup
0
1
Name
RESERVED
96/100M Clock Speed
5
1
RESERVED
4
1
RESERVED
3
1
PCI5
2
1
PCI4
1
1
PCI3
0
1
PCI2
Byte 14: Control Register 14
Bit
7
6
5
4
@Pup
1
0
0
0
Name
RESERVED
RESERVED
RESERVED
CLKREQ#A
Description
RESERVED Set = 0
RESERVED
RESERVED
RESERVED
27-MHz (spread and non-spread) Output Drive Strength
0 = Low, 1 = High
RESERVED Set = 0
RESERVED Set = 0
RESERVED
CLKREQ#A Enable
0 = Disable 1 = Enable
CLKREQ#B Enable
0 = Disable 1 = Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Description
Description
RESERVED
96/100 SRC Clock Speed
0 = 96 MHz, 1 = 100 MHz
RESERVED, Set = 1
RESERVED, Set = 1
PCI5 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI4 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI3 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
PCI2 (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
Description
RESEREVD
RESERVED
RESERVED
SRC[T/C]5 Control
0 = SRC[T/C]5 not stoppable by CLKREQ#A
1 = SRC[T/C]5 stoppable by CLKREQ#A
Document #: 38-07716 Rev *C
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