CY27410 Datasheet, PDF (15/29 Pages) Cypress Semiconductor – RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset

CY27410
DC Output Specifications
Table 8. DC Specifications for LVCMOS Output
Symbol
V_OH
V_OL
Description
Output high voltage
Output low voltage
4-mA load
4-mA load
Conditions
Min
Typ
V_DDIO – 0.3 –
–
–
Max Units
–
V
0.3
V
Table 9. DC Specifications for LVDS Output (V_DDIO = 2.5-V or 3.3-V range)
Symbol
Description
Conditions
V_PP
LVDS output AC single-ended 8 MHz to 325 MHz
pk-pk,
V_PP
LVDS output AC single-ended 325 MHz to 700 MHz
pk-pk
V_PP
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V_OCM
Output common-mode voltage Met only at 2.5 V and 3.3 V. Need AC coupling
for 1.8-V operation
V_OCM
Change in VOCM between
complementary output states
I_OZ
Output leakage current
Output off, V_OUT = 0.75 V to 1.75 V
Min
250
200
–
1.125
–
–20
Typ Max Units
–
510 mV
–
510 mV
–
50 mV
1.200 1.375 V
–
50 mV
–
20 A
Table 10. DC Specifications for LVPECL Output (V_DDIO = 2.5-V or 3.3-V range)
Symbol
V_OH
V_OL
V_PP
Description
Output high voltage
Output low voltage
LVPECL output AC single
ended pk-pk,
Conditions
Min
Typ
Max
Units
R-term = 50  to V_TT (V_DDIO – 2.0 V) V_DDIO – 1.165 – V_DDIO – 0.800 V
R-term = 50  to V_TT (V_DDIO – 2.0 V) V_DDIO – 2.0 – V_DDIO – 1.620 V
f_OUT = 8 MHz to 150 MHz
450
–
–
mV
f_OUT = 150 MHz to 700 MHz
320
–
–
mV
Table 11. DC Specifications for CML Output (V_DDIO = 2.5-V or 3.3-V range)
Symbol
V_OH
V_OL
V_PP
V_PP
Description
Output high voltage
Output low voltage
CML output AC single-ended
pk-pk
CML output AC single-ended
pk-pk
Conditions
R-term= 50  to V_DDIO
R-term= 50  to V_DDIO
f_OUT = 8 MHz to150 MHz
150 < f_OUT < 700 MHz
Min
Typ
Max
Units
V_DDIO – 0.1 –
–
V
V_DDIO – 0.7
–
V_DDIO – 0.3 V
250
–
700
mV
200
–
600
mV
Document Number: 001-89074 Rev. *K
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