CY27410 Datasheet, PDF (1/29 Pages) Cypress Semiconductor – RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset

CY27410
4-PLL Spread-Spectrum Clock Generator
4-PLL Spread-Spectrum Clock Generator
Features
■ Input frequencies
❐ Crystal input: 8 MHz to 48 MHz
❐ Reference clock: 8 MHz to 250 MHz LVCMOS
❐ Reference clock: 8 MHz to 700 MHz differential
■ Output frequencies
❐ 25 MHz to 700 MHz LVDS, LVPECL, HCSL, CML
❐ 3 MHz to 250 MHz LVCMOS
❐ 1 kHz to 8 MHz for one LVCMOS output
■ RMS phase jitter: 1-ps max at 12-kHz to 20-MHz offset
■ PCIe 1.0/2.0/3.0 compliant
■ SATA 2.0, USB 2.0/3.0, 1/10-GbE compliant
Logic Block Diagram
■ Maximum 12 outputs split in two banks with six outputs each.
❐ Up to eight differential output pairs (HCSL, LVPECL, CML,
or LVDS)
❐ Up to 12 LVCMOS outputs
■ Up to 100-ps skew for differential outputs within a bank
■ Four fractional N-type phase-locked loops (PLLs) with
❐ VCXO (±120 ppm with steps of 0.23 ppm)
❐ Spread-spectrum capability (Logic SS and Lexmark profile
0.1% to 5% in 0.1% steps, down or center spread)
■ Supply voltage: 1.8 V, 2.5 V, and 3.3 V
■ Zero-delay buffer (ZDB) and non-zero delay buffer (NZDB)
configurations
■ I²C configurable with onboard programming
■ Industrial-grade device, offered in 48-pin QFN (7 × 7 × 1.0 mm)
package
XIN
XOUT
IN1P
IN1N
IN2P
IN2N
Reference
System
INI
IN1S
IN2S
INC
Output Drivers 1
O1[1..4]
PLL1
O2[1..4]
PLL2
PLL3
O3[1..4]
PLL4
O4[1..4]
Output Drivers 2
Register
Memory
NV
Memory
PRG
Block
ADC
FS
I2C
RCAL
VIN
FS2
FS1
FS0
SCLK
SDAT
RCCAL
BG
OSC
POR
QP
LDOs
VDD
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-89074 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 14, 2016