CY7C63310 Datasheet, PDF (14/83 Pages) Cypress Semiconductor – enCoRe™ II Low-Speed USB Peripheral Controller

CY7C63310, CY7C638xx
9.2 Data Memory Organization
The CY7C63310/638xx microcontrollers provide up to 256 bytes of data RAM.
after reset
8-bit PSP
Figure 9-2. Data Memory Organization
Address
0x00
Stack begins here and grows upward.
Top of RAM Memory
0xFF
9.3 Flash
This section describes the Flash block of the enCoRe II. Much of
the user visible Flash functionality including programming and
security are implemented in the M8C Supervisory Read Only
Memory (SROM). The enCoRe II Flash has an endurance of
1000 cycles and a 10 year data retention capability.
9.3.1 Flash Programming and Security
All Flash programming is performed by code in the SROM. The
registers that control the Flash programming are only visible to
the M8C CPU when it executes out of SROM. This makes it
impossible to read, write or erase the Flash by bypassing the
security mechanisms implemented in the SROM.
Customer firmware can program the Flash only through SROM
calls. The data or code images are sourced through any interface
with the appropriate support firmware. This type of programming
requires a ‘boot-loader’, which is a piece of firmware resident on
the Flash. For safety reasons this boot-loader must not be
overwritten during firmware rewrites.
The Flash provides four extra auxiliary rows that are used to hold
Flash block protection flags, boot time calibration values,
configuration tables, and any device values. The routines for
accessing these auxiliary rows are documented in the section
SROM on page 14 section. The auxiliary rows are not affected
by the device erase function.
9.3.2 In System Programming
Most designs that include an enCoRe II part have a USB
connector attached to the USB D+ and D– pins on the device.
These designs require the ability to program or reprogram a part
through the USB D+ and D– pins alone.
The enCoRe II devices enable this type of in system
programming by using the D+ and D– pins as the serial
programming mode interface. This allows an external controller
to enable the enCoRe II part to enter the serial programming
mode, and then use the test queue to issue Flash access
functions in the SROM. The programming protocol is not USB.
9.4 SROM
The SROM holds code that boots the part, calibrates circuitry,
and performs Flash operations (Table 9-1 on page 14 lists the
SROM functions). The functions of the SROM are accessed in
the normal user code or operating from Flash. The SROM exists
in a separate memory space from the user code. The SROM
functions are accessed by executing the Supervisory System
Call instruction (SSC), which has an opcode of 00h. Before
executing the SSC the M8C’s accumulator must be loaded with
the desired SROM function code from Table 9-1 on page 14.
Undefined functions cause a HALT if called from the user code.
The SROM functions are executing code with calls; as a result,
the functions require stack space. With the exception of Reset,
all of the SROM functions have a parameter block in SRAM that
must be configured before executing the SSC. Table 9-2 on page
15 lists all possible parameter block variables. The meaning of
each parameter, with regards to a specific SROM function, is
described later in this section.
Table 9-1. SROM Function Codes
Function Code
Function Name
00h
SWBootReset
01h
ReadBlock
02h
WriteBlock
03h
EraseBlock
05h
EraseAll
06h
TableRead
07h
CheckSum
Stack Space
0
7
10
9
11
3
3
Document 38-08035 Rev. *J
Page 14 of 83
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