CY7C63310 Datasheet, PDF (12/83 Pages) Cypress Semiconductor – enCoRe™ II Low-Speed USB Peripheral Controller

CY7C63310, CY7C638xx
8. Instruction Set Summary
The instruction set is summarized in Table 8-1 numerically and serves as a quick reference. If more information is needed, the
Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the
Cypress web site at http://www.cypress.com).
Table 8-1. Instruction Set Summary Sorted Numerically by Opcode Order^{[2, 3]}
Instruction Format
Flags
Instruction Format
Flags
Instruction Format
00 15 1 SSC
2D 8 2 OR [X+expr], A
Z
5A 5 2 MOV [expr], X
01 4 2 ADD A, expr
C, Z
2E 9 3 OR [expr], expr
Z
5B 4 1 MOV A, X
02 6 2 ADD A, [expr]
C, Z
2F 10 3 OR [X+expr], expr
Z
5C 4 1 MOV X, A
03 7 2 ADD A, [X+expr]
C, Z
30 9 1 HALT
5D 6 2 MOV A, reg[expr]
04 7 2 ADD [expr], A
C, Z
31 4 2 XOR A, expr
Z
5E 7 2 MOV A, reg[X+expr]
05 8 2 ADD [X+expr], A
C, Z
32 6 2 XOR A, [expr]
Z
5F 10 3 MOV [expr], [expr]
06 9 3 ADD [expr], expr
C, Z
33 7 2 XOR A, [X+expr]
Z
60 5 2 MOV reg[expr], A
07 10 3 ADD [X+expr], expr
C, Z
34 7 2 XOR [expr], A
Z
61 6 2 MOV reg[X+expr], A
08 4 1 PUSH A
35 8 2 XOR [X+expr], A
Z
62 8 3 MOV reg[expr], expr
09 4 2 ADC A, expr
C, Z
36 9 3 XOR [expr], expr
Z
63 9 3 MOV reg[X+expr], expr
0A 6 2 ADC A, [expr]
C, Z
37 10 3 XOR [X+expr], expr
Z
64 4 1 ASL A
0B 7 2 ADC A, [X+expr]
C, Z
38 5 2 ADD SP, expr
65 7 2 ASL [expr]
0C 7 2 ADC [expr], A
C, Z
39 5 2 CMP A, expr
66 8 2 ASL [X+expr]
0D 8
0E 9
0F 10
2 ADC [X+expr], A
3 ADC [expr], expr
3 ADC [X+expr], expr
C, Z
3A 7 2 CMP A, [expr]
C, Z
3B 8 2 CMP A, [X+expr]
C, Z
3C 8 3 CMP [expr], expr
67 4 1 ASR A
if (A=B) Z=1
68 7 2 ASR [expr]
if (A<B) C=1
69 8 2 ASR [X+expr]
10 4 1 PUSH X
3D 9 3 CMP [X+expr], expr
6A 4 1 RLC A
11 4 2 SUB A, expr
C, Z
3E 10 2 MVI A, [ [expr]++]
Z
6B 7 2 RLC [expr]
12 6 2 SUB A, [expr]
C, Z
3F 10 2 MVI [ [expr]++], A
6C 8 2 RLC [X+expr]
13 7 2 SUB A, [X+expr]
C, Z
40 4 1 NOP
6D 4 1 RRC A
14 7 2 SUB [expr], A
C, Z
41 9 3 AND reg[expr], expr
Z
6E 7 2 RRC [expr]
15 8 2 SUB [X+expr], A
C, Z
42 10 3 AND reg[X+expr], expr
Z
6F 8 2 RRC [X+expr]
16 9 3 SUB [expr], expr
C, Z
43 9 3 OR reg[expr], expr
Z
70 4 2 AND F, expr
17 10 3 SUB [X+expr], expr
C, Z
44 10 3 OR reg[X+expr], expr
Z
71 4 2 OR F, expr
18 5 1 POP A
Z
45 9 3 XOR reg[expr], expr
Z
72 4 2 XOR F, expr
19 4 2 SBB A, expr
C, Z
46 10 3 XOR reg[X+expr], expr
Z
73 4 1 CPL A
1A 6 2 SBB A, [expr]
C, Z
47 8 3 TST [expr], expr
Z
74 4 1 INC A
1B 7 2 SBB A, [X+expr]
C, Z
48 9 3 TST [X+expr], expr
Z
75 4 1 INC X
1C 7 2 SBB [expr], A
C, Z
49 9 3 TST reg[expr], expr
Z
76 7 2 INC [expr]
1D 8 2 SBB [X+expr], A
C, Z
4A 10 3 TST reg[X+expr], expr
Z
77 8 2 INC [X+expr]
1E 9 3 SBB [expr], expr
C, Z
4B 5 1 SWAP A, X
Z
78 4 1 DEC A
1F 10 3 SBB [X+expr], expr
C, Z
4C 7 2 SWAP A, [expr]
Z
79 4 1 DEC X
20 5 1 POP X
4D 7 2 SWAP X, [expr]
7A 7 2 DEC [expr]
21 4 2 AND A, expr
Z
4E 5 1 SWAP A, SP
Z
7B 8 2 DEC [X+expr]
22 6 2 AND A, [expr]
Z
4F 4 1 MOV X, SP
7C 13 3 LCALL
23 7 2 AND A, [X+expr]
Z
50 4 2 MOV A, expr
Z
7D 7 3 LJMP
24 7 2 AND [expr], A
Z
51 5 2 MOV A, [expr]
Z
7E 10 1 RETI
25 8 2 AND [X+expr], A
Z
52 6 2 MOV A, [X+expr]
Z
7F 8 1 RET
26 9 3 AND [expr], expr
Z
53 5 2 MOV [expr], A
8x 5 2 JMP
27 10 3 AND [X+expr], expr
Z
54 6 2 MOV [X+expr], A
9x 11 2 CALL
28 11 1 ROMX
Z
55 8 3 MOV [expr], expr
Ax 5 2 JZ
29 4 2 OR A, expr
Z
56 9 3 MOV [X+expr], expr
Bx 5 2 JNZ
2A 6 2 OR A, [expr]
Z
57 4 2 MOV X, expr
Cx 5 2 JC
2B 7 2 OR A, [X+expr]
Z
58 6 2 MOV X, [expr]
Dx 5 2 JNC
2C 7 2 OR [expr], A
Z
59 7 2 MOV X, [X+expr]
Ex 7 2 JACC
Fx 13 2 INDEX
Notes
2. Interrupt routines take 13 cycles before execution resumes at interrupt vector table.
3. The number of cycles required by an instruction is increased by one for instructions that span 256 byte boundaries in the Flash memory space.
Flags
Z
Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
C, Z
Z
Document 38-08035 Rev. *J
Page 12 of 83
[+] Feedback