CY28326 Datasheet, PDF (14/23 Pages) Cypress Semiconductor – FTG for VIA PT880 Serial Chipset

CY28326
F S[D :A]
VTT_PWRGD
PWRGD_VRM
VDD Clock Gen
Clock State
State 0
Off
C lo ck O u tp u ts
Off
Clock VCO
0.2-0.3mS
D e la y
State 1
Wait for
VTT_PWRGD
Sample Sels
State 2
On
Device is not affected,
VTT_PWRGD is ignored.
And this pin become PD#
fu n c tio n
State 3
On
Figure 9. VTT_PWRGD Timing Diagram
VDD_A = 2.0V
S0
Power Off
S1
Delay
>0.25mS
VTT_PWRGD = High
S2
Sample
Inputs straps
VDD_A = off
S3
Normal
Operation
VTT_PWRGD = toggle
Wait for <1.8ms
Enable Outputs
Figure 10. Clock Generator Power-up/Run State Diagram
Document #: 38-07616 Rev. *A
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