CY28326 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – FTG for VIA PT880 Serial Chipset

CY28326
FTG for VIA PT880 Serial Chipset
Features
• Supports P4^ CPUs
• 3.3V power supply
• Ten copies of PCI clocks
• One 48 MHz USB clock
• Two copies of 25 MHz for SRC/LAN clocks
• One 48 MHz/24 MHz programmable SIO clock
Block Diagram
• Three differential CPU clock pairs
• SMBus support with Byte Write/Block Read/Write
capabilities
• Spread Spectrum EMI reduction
• Dial-A-Frequency^® features
• Auto Ratio features
• 48-pin SSOP package
Pin Configuration^[1]
XIN
XOUT
PLL1
CPU_STP#
IREF
FS[A:D]
Power
on
Latch
VTTPWRGD#
/2
PCI_STP#
MODE
PLL2
PD#
SDATA
SCLK
WD
Logic
I2C
Logic
REF[0:2]
CPUT[0:2]
CPUC[0:2]
25MHz[0:1]
AGP[0:2]
PCI[0:6]
PCI_F[0:2]
48MHz
24_48MHz
SRESET
**FSA/REF0
**FSB/REF1
VDDREF
XIN
XOUT
VSSREF
*FSC/PCIF0
*FSD/PCIF1
*Mode/PCIF2
VDDPCI
VSSPCI
PCI0
PCI1
PCI2
PCI3
PCI4
VDDPCI
VSSPCI
*(PCI_STP#)/Ratio0/PCI5
*(CPU_STP#)/Ratio1/PCI6
48MHz
**24_48_SEL/24_48MHz
VSS48
VDD48
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
48 Pin SSOP
VDDA
VSSA
IREF
CPUT2
CPUC2
VSSCPU
CPUT1
CPUC1
VDDCPU
CPUT0
CPUC0
VSSSRC
25MHz1
25MHz0
VDDSRC
*VTT_PWRGD/*PD#
SDATA
SCLK
SRESET#
AGP2
VSSAGP
VDDAGP
AGP1/*RatioSel
AGP0
Note:
1. Pins marked with [*] have internal 150kΩ pull-up resistors. Pins marked with [**] have internal 150kΩ pull-down resistors.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07616 Rev. *A
Revised June 22, 2004