MB39C604 Datasheet, PDF (13/36 Pages) Cypress Semiconductor – PSR topology in an isolated flyback circuit

MB39C604
8.4 Power-On Sequence
When the AC line voltage is supplied, V_BULK is powered from the AC line through a diode bridge, and the VDD pin is charged from
V_BULK through an external source-follower BiasMOS.(Figure 8 red path)
When the VDD pin is charged up and the voltage on the VDD pin (V_VDD) rises above the UVLO threshold voltage, an internal Bias
circuit starts operating, and MB39C604 starts the dimming control. After the UVLO is released, this device enables switching and is
operating in a forced switching mode (T_ON = 1.5 µs, T_OFF = 78 µs to 320 µs). When the voltage on the TZE pin reaches the Zero
energy threshold voltage (V_TZETH = 0.7V), MB39C604 enters normal operation mode. After the switching begins, the VDD pin is also
charged from Auxiliary Winding through an external diode (DBIAS).(Figure 8 blue path)
Around zero cross points of the AC line voltage V_VDD is not supplied from V_BULK or Auxiliary Winding. It is necessary to set an
appropriate capacitor of the VDD pin in order to keep V_VDD above the UVLO threshold voltage in this period. An external diode (D1)
between BiasMOS and the VDD pin is used to prevent discharge from the VDD pin to V_BULK at the zero cross points.
Figure 8. VDD Supply Path at Power-On
Figure 9. Power-On Waveform
V_BULK
UVLO Vth = 13V
VDD
Force switching (T_ON=1.5us/T_OFF=78us～320us)
Switching start
DRV
VLED
TZE
V_TZETH = 0.7V
Normal switching
Document Number: 002-08441 Rev.*A
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