CY7C451 Datasheet, PDF (13/24 Pages) Cypress Semiconductor – 512x9 2Kx9 and 4Kx9 Cascadable Clocked FIFOs with Programmable

CY7C451
CY7C453
CY7C454
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks^[22,27,30]
COUNT 2031 2032
[495] [496]
2031
[495]
2030
[494]
2030 (no change)
[494]
FLAG UPDATE CYCLE
2031
[495]
2032
[496]
CKW
W1
W2
ENABLED
WRITE
W3
W4
W5
W6
FLAG
UPDATE
ENABLED
WRITE
ENABLED
WRITE
WRITE
ENW
t_SKEW1
t_SKEW2
CKR
R1
R2
R3
R4
R5
R6
ENABLED
ENABLED
READ
READ
ENR
2033
[497]
W7
ENABLED
WRITE
R7
HF
E/F
PAFE
LOW
HIGH
t_FD
t_FD
t_FD
[22,23,30,37]
Write to Full Flag Timing Diagram with Free-Running Clocks
COUNT
2047
[511]
2048
[512]
2047
[511]
LATENT CYCLE
2048
[512]
CKW
ENW
W1
ENABLED
WRITE
W2
IGNORED
WRITE
W3
IGNORED
WRITE
t_SKEW2
W4
FLAG
UPDATE
WRITE
W5
ENABLED
WRITE
t_SKEW1
t_SKEW2
CKR
R1
R2
R3
R4
R5
ENABLED
READ
ENR
C451-19
W6
IGNORED
WRITE
R6
LOW
HF
t_FD
E/F
LOW
PAFE
t_FD
t_FD
C451-20
Notes:
37. W2 is ignored because the FIFO is full (count = 4096[2048,512]). It is important to note that W3 is also ignored because R3, the first enabled read after full,
occurs less than t_SKEW2 before W3. Therefore, the FIFO still appears full when W3 occurs. Because R3 occurs greater than t_SKEW2 before W4, W4
includes R3 in the flag update.
Document #: 38-06033 Rev. *A
Page 13 of 24