W311 Datasheet, PDF (12/19 Pages) Silicon Laboratories – FTG for VIA™ Pro-266 DDR Chipset

W311
Byte 17: Reserved Register
Bit
Bit 2
Bit 1
Bit 0
Pin#
-
-
-
Name
Vendor test mode
Vendor test mode
Vendor test mode
Default
0
0
0
Description
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Reserved. Write with ‘0’.
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
FS4
FS3
FS2
FS1
FS0
SEL4
SEL3
SEL2
SEL1
SEL0
CPU
3V66
PCI
0
0
0
0
0
200.0
66.6
33.3
0
0
0
0
1
190.0
76.0
38.0
0
0
0
1
0
180.0
72.0
36.0
0
0
0
1
1
170.0
68.0
34.0
0
0
1
0
0
166.0
66.4
33.2
0
0
1
0
1
160.0
64.0
32.0
0
0
1
1
0
150.0
75.0
37.5
0
0
1
1
1
145.0
72.5
36.3
0
1
0
0
0
140.0
70.0
35.0
0
1
0
0
1
136.0
68.0
34.0
0
1
0
1
0
130.0
65.0
32.5
0
1
0
1
1
124.0
62.0
31.0
0
1
1
0
0
66.6
66.6
33.3
0
1
1
0
1
100.0
66.6
33.3
0
1
1
1
0
118.0
78.7
39.3
0
1
1
1
1
133.3
66.6
33.3
1
0
0
0
0
66.8
66.8
33.4
1
0
0
0
1
100.2
66.8
33.4
1
0
0
1
0
115.0
76.7
38.3
1
0
0
1
1
133.6
66.8
33.4
1
0
1
0
0
66.8
66.8
33.4
1
0
1
0
1
100.2
66.8
33.4
1
0
1
1
0
110.0
73.3
36.7
1
0
1
1
1
133.6
66.8
33.4
1
1
0
0
0
105.0
70.0
35.0
1
1
0
0
1
90.0
60.0
30.0
1
1
0
1
0
85.0
56.7
28.3
1
1
0
1
1
78.0
78.0
39.0
1
1
1
0
0
66.6
66.6
33.3
1
1
1
0
1
100.0
66.6
33.3
1
1
1
1
0
75.0
75.0
37.5
1
1
1
1
1
133.3
66.6
33.3
PLL Gear Con-
stants
(G)
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
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