CY8C32_1105 Datasheet, PDF (119/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 50 MHz operation

PSoC^® 3: CY8C32 Family
Data Sheet
Description Title: PSoC^® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC^®)
Document Number: 001-56955
*J
3200146 03/28/2011 MKEA Removed Preliminary status from the data sheet.
Updated JTAG ID
Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table
Updated JTAG Interface AC Specifications and SWD Interface Specifications
tables
Updated USBIO DC specs
Added 0.01 to max speed
Updated Features on page 1
Added Section 5.5, Nonvolatile Latches
Updated Flash AC specs
Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables
Add reference to application note AN58304 in section 8.1
Updated 100-pin TQFP package spec
Added oscillator, I/O, VDAC, regulator graphs
Updated JTAG/SWD timing diagrams
Updated GPIO and SIO AC specs
Updated POR with Brown Out AC spec table
UpdatedIDAC graphs
Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing
diagrams
Added full chip performance graphs
Changed MHzECO range.
Added “Solder Reflow Peak Temperature” table.
*K
3259185 05/17/2011 MKEA Added JTAG and SWD interface connection diagrams
Updated T_JAand T_JC values in Table 13-1
Changed typ and max values for the TCVos parameter in Opamp DC
specifications table.
Updated Clocking subsystem diagram.
Changed Vssd to Vssb in the PSoC Power System diagram
Updated Ordering information.
Document Number: 001-56955 Rev. *K
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