CY8C32_1105 Datasheet, PDF (114/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 50 MHz operation

PSoC^® 3: CY8C32 Family
Data Sheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
PHUB
PHY
PICU
PLA
PLD
PLL
PMDD
POR
PRES
PRS
PS
PSoC^®
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
RTR
RX
SAR
SC/CT
SCL
SDA
S/H
SINAD
SIO
SOC
Description
peripheral hub
physical layer
port interrupt control unit
programmable logic array
programmable logic device, see also PAL
phase-locked loop
package material declaration datasheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
register transfer language
remote transmission request
receive
successive approximation register
switched capacitor/continuous time
I²C serial clock
I²C serial data
sample and hold
signal to noise and distortion ratio
special input/output, GPIO with advanced
features. See GPIO.
start of conversion
Table 14-1. Acronyms Used in this Document (continued)
Acronym
SOF
SPI
SR
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
TX
UART
UDB
USB
Description
start of frame
Serial Peripheral Interface, a communications
protocol
slew rate
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
Universal Asynchronous Transmitter Receiver, a
communications protocol
universal digital block
Universal Serial Bus
USBIO
VDAC
USB input/output, PSoC pins used to connect to
a USB port
voltage DAC, see also DAC, IDAC
WDT
WOL
WRES
watchdog timer
write once latch, see also NVL
watchdog timer reset
XRES
XTAL
external reset I/O pin
crystal
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 3 Registers TRM
Document Number: 001-56955 Rev. *K
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