CY8C32_1105 Datasheet, PDF (10/120 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC) DC to 50 MHz operation

PSoC^® 3: CY8C32 Family
Data Sheet
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
Vssa
Vddd
Vssd
Vdda
Vssd
Plane
Vssa
Plane
3. Pin Descriptions
IDAC0
Low resistance output pin for high current DAC (IDAC).
Extref0, Extref1
External reference input to the analog system.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense.
I2C0: SCL, I2C1: SCL
I²C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I²C SCL if wake from sleep is not
required.
I2C0: SDA, I2C1: SDA
I²C SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I²C SDA if wake from sleep is not
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25- MHz crystal oscillator pin.
nTRST
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
SIO
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK
Serial wire debug clock programming and debug port
connection.
SWDIO
Serial wire debug input and output programming and debug port
connection.
SWV.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
Document Number: 001-56955 Rev. *K
Page 10 of 120