CYK256K16SCCB Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 4-Mbit (256K x 16) Pseudo Static RAM

CYK256K16SCCB
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Advanced low-power MoBL^® architecture
• High speed: 55 ns, 60 ns and 70 ns
• Wide voltage range: 2.7V to 3.3V
• Typical active current: 1 mA @ f = 1 MHz
• Low standby power
• Automatic power-down when deselected
Functional Description^[1]
The CYK256K16SCCB is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 16 bits that
supports an asynchronous memory interface. This device
features advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life™ (MoBL)
in portable applications such as cellular telephones. The
device can be put into standby mode reducing power
consumption dramatically when deselected (CE₁ LOW, CE₂
HIGH or both BHE and BLE are HIGH). The input/output pins
(I/O₀ through I/O₁₅) are placed in a high-impedance state
when: deselected (CE₁ HIGH, CE₂ LOW, OE is deasserted
HIGH), or during a write operation (Chip Enabled and Write
Enable WE LOW).
Reading from the device is accomplished by asserting the
Chip Enables (CE₁ LOW and CE₂ HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins A₀ through A₁₇ will appear on
I/O₀ to I/O₇. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O₈ to I/O₁₅. See the Truth Table for a
complete description of read and write modes.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
256K x 16
RAM Array
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power -Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE₂
CE₁
CE₂
CE₁
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05526 Rev. *H
Revised October 18, 2006
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