CYII5SM1300AB_11 Datasheet, PDF (1/35 Pages) Cypress Semiconductor – IBIS5 1.3 Megapixel CMOS Image Sensor

CYII5SM1300AB
IBIS5 1.3 Megapixel CMOS Image Sensor
Features
■ 1280 × 1024 active pixels
■ 6.7 μm × 6.7 μm square pixels
■ 2/3” optical format
■ Global and rolling shutter
■ Master clock: 40 MHz
■ 27 fps (1280 × 1024) and 106 fps (640 × 480)
■ On-chip 10-bit ADCs
■ Serial peripheral interface (SPI)
■ Windowing (ROI)
■ Sub-sampling: 1:2 mode
■ Supply voltage
❐ Analog: 3.0 V to 4.5 V
❐ Digital: 3.3 V
❐ I/O: 3.3 V
■ Power consumption: 200 mW
■ 0 °C to +65 °C operating temperature range
■ 84-pin LCC package
Applications
■ Machine vision
■ Inspection
■ Robotics
■ Traffic monitoring
Description
The IBIS5-B-1300 is a solid state CMOS image sensor that
integrates the functionality of complete analog image acquisition,
digitizer, and digital signal processing system on a single chip.
This 1.3-mega pixel (1280 × 1024) CMOS active pixel sensor
dedicated to industrial vision applications features both rolling
and snapshot (or global) shutter. Full frame readout time is 36 ms
(max. 27.5 fps), and readout speed are boosted by windowed
region of interest (ROI) readout. Another feature includes the
double and multiples slope functionality to capture high dynamic
range scenes. The sensor is available in a monochrome version
or Bayer (RGB) patterned color filter array.
User programmable row and column start/stop positions allow
windowing down to a 2×1 pixel window for digital zoom. Sub
sampling or viewfinder mode reduces resolution while
maintaining the constant field of view and an increased frame
rate. An on-chip analog signal pipeline processes the analog
video output of the pixel array. Double sampling (DS) eliminates
the fixed pattern noise. The programmable gain and offset
amplifier maps the signal swing to the ADC input range. A 10-bit
ADC converts the analog data to a 10-bit digital word stream. The
sensor uses a 3-wire serial peripheral interface (SPI), or a 16-bit
parallel interface. It operates with a 3.3 V power supply and
requires only one master clock for operation up to 40 MHz. It is
housed in an 84-pin ceramic LCC package.
Figure 1. IBIS5-B-1300 Photo
Ordering Information
See Ordering Code Information on page 33 for more information.
Marketing Part Number
Description
CYII5SM1300AB-QDC
CYII5SM1300AB-QWC
Mono with glass
Mono without glass
CYII5SC1300AB-QDC
CYII5FM1300AB-QDC
Color with glass
Mono with thicker epi with glass
Package
84-pin LCC
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05710 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 13, 2011
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