|
FX589 Datasheet, PDF (7/18 Pages) CML Microcircuits – Low-Voltage/High-Speed GMSK Modem | |||
|
◁ |
Application Information ......
PLLacq
â1â
Rx Hold
PLL Action
X Acquire: Sets the PLL bandwidth wide enough to allow a lock to the received signal in
less than 8 zero crossings. This mode will operate as long as PLLacq is a logic â1â.
â1â to â0â
â1â Medium Bandwidth: The correction applied to the extracted clock is limited to a
maximum of ±1/16th bit-period for every two received zero-crossings. The PLL operates
in this mode for a period of about 30 bits immediately following a â1â to â0â transition of the
PLLacq input, provided that the Rx Hold input is a logic â1â.
â0â
â1â Narrow Bandwidth: The correction applied to the extracted clock is limited to a maximum
of ±1/64th bit-period for every two received zero-crossings. The PLL operates in this
mode whenever the Rx Hold Input is a logic â1â and PLLacq has been a logic â0â for at
least 30 bit periods (after Medium Bandwidth operation for instance).
â0â
â0â Hold: The PLL feedback loop is broken, allowing the Rx Clock to freewheel during signal
fade periods.
RxDCacq Rx Hold
Rx Level Measure Action
â0â to â1â
X Clamp: Operates for one bit-time after a â0â to â1â transition of the RxDCacq input. The
external capacitors are rapidly charged towards a voltage mid-way between the received
signal input level and V , with the charge time-constant being of the order of 0.5bit-time.
BIAS
â1â
X Fast Peak Detect: The voltage detectors act as peak-detectors, one capacitor is used to
capture the âpositiveâ-going signal peaks of the Rx Filter output signal and the other capturing
the ânegativeâ-going peaks. The detectors operate in this mode whenever the RxDCacq input
is at a logic â1,â except for the initial 1-bit Clamp-mode time.
â0â
â1â Averaging Peak Detect: Provides a slower but more accurate measurement of the signal
peak amplitudes.
â0â
â0â Hold: The capacitor charging circuits are disabled so that the outputs of the voltage detectors
remain substantially at the last readings (discharging very slowly [time-constant approx.
2,000bits] towards VBIAS).
Table 2 PLL and Rx Level Measurement Operational Modes
X = don't care
Rx Clock Extraction
Synchronized by a phased locked loop (PLL)
circuit to zero-crossings of the incoming data, the âRx
Clock Extractionâ circuitry controls the âRx Clockâ
output. The Rx Clock is also used internally by the
Data Extraction circuitry. The PLL parameters can be
varied by the âRx Circuit Controlâ inputs PLLacq and Rx
Hold to operate in one of four PLL modes as described
in Table 2.
Rx Data Extraction
The âRx Data Extractionâ circuit decides whether
each received bit is a â1â or â0â by sampling the output
of the Rx Filter in the middle of each bit-period, and
comparing the sampled voltage against a threshold
derived from the âLevel Measuringâ circuit. This
threshold is varied on a bit-by-bit basis to compensate
for intersymbol interference depending on the chosen
BT. The extracted data is output from the âRx Dataâ
pin, and should be sampled externally on the rising
edge of the âRx Clock.â
Rx S/N Detection
The âRx S/N Detectorâ system classifies the
incoming zero-crossings as GOOD or BAD depending
upon the time when each crossing actually occurs with
respect to its expected time as determined by the
Clock Extraction PLL. This information is then
processed to provide a logic level output at the âRx
S/Nâ pin; a âhighâ level indicates a series of GOOD
crossings, a âlowâ level indicates a BAD crossing.
By averaging this output it is possible to derive a
measure of the Signal-to-Noise-Ratio and hence the
Bit-Error-Rate of the received signal.
7
|
▷ |